[avr-gcc-list] re-initialising an ATMega128 as much as possible (without real reset)

[Torsten Mohr]

Hi,

i program an ATMega128, there's a bootloader at 0x1e000
and a normal application at 0x00000.

When the application starts the bootloader, it does that
by directly jumping into it.

In the bootloader i'd like to un-initialise as much of
the micro as possible, i think it is not possible to
initialise everything the same way as after a real reset.

For this i wrote a function that does:

cli()
wdt_disable()

After that it goes through a list of lots of special
function registers and assigns them values.  I have
attached that list at the end of this message, maybe
this is of interest for anybody else.

The list of the registers is at the moment ordered
by the addresses of the registers.

But i think it makes more sense to do this based on
rules, like:

+ First disable the interrupts by setting the *MSK
registers, then clear the interrupt flags with the
*FR registers.


I have lots of questions now:

1. Is this the way to go when i don't want to generate a real
reset?  What else do i need to do?

2.
Is the cli() and wdt_disable() ok?

3.
What would be the rules for the order of the special
function registers to assign values to them?  Are there
any other general rules like the one above?

4.
What are the things that are NOT initialised correctly that
way?



Best regards,
Torsten.


Here's the list of the registers and how i initialise them
at the moment:


#define VOID_UNDEF ((void*)0)

#define IS(addr, val) {(uint8_t*)&addr, val}


typedef struct {
  uint8_t* addr;
  uint8_t val;
} INIT_AVR;


INIT_AVR init_mega128_is[] = {
  IS(DDRE, 0x00),
  IS(PORTE, 0x00),
  IS(ADCSRA, 0x00),
  IS(ADMUX, 0x00),
  IS(ACSR, 0x00),
  IS(UBRR0L, 0x00),
  IS(UCSR0B, 0x00),
  IS(UCSR0A, 0x00),
  //  IS(UDR0, 0x00),
  IS(SPCR, 0x00),
  IS(SPSR, 0x00),
  //  IS(SPDR, 0x00),
  IS(DDRD, 0x00),
  IS(PORTD, 0x00),
  IS(DDRC, 0x00),
  IS(PORTC, 0x00),
  IS(DDRB, 0x00),
  IS(PORTB, 0x00),
  IS(DDRA, 0x00),
  IS(PORTA, 0x00),
  IS(EECR, 0x00),
  IS(EEDR, 0x00),
  IS(SFIOR, 0x00),
  //  IS(WDTCR, 0x00),
  //  IS(OCDR, 0x00),
  IS(OCR2, 0x00),
  IS(TCNT2, 0x00),
  IS(TCCR2, 0x00),
  IS(ICR1L, 0x00),
  IS(ICR1H, 0x00),
  IS(OCR1BL, 0x00),
  IS(OCR1BH, 0x00),
  IS(OCR1AL, 0x00),
  IS(OCR1AH, 0x00),
  IS(TCNT1L, 0x00),
  IS(TCNT1H, 0x00),
  IS(TCCR1B, 0x00),
  IS(TCCR1A, 0x00),
  IS(OCR0, 0x00),
  IS(TCNT0, 0x00),
  IS(TCCR0, 0x00),
  //  IS(MCUCSR, 0x00),
  IS(MCUCR, 0x00),
  IS(TIFR, 0xFF), // 0xFF
  IS(TIMSK, 0x00),
  IS(EIFR, 0xFF), // 0xFF
  IS(EIMSK, 0x00),
  IS(EICRB, 0x00),
  IS(RAMPZ, 0x00),
  IS(XDIV, 0x00),
  //  IS(SPL, 0x00),
  //  IS(SPH, 0x00),
  IS(SREG, 0x00),
  IS(DDRF, 0x00),
  IS(PORTF, 0x00),
  IS(DDRG, 0x00),
  IS(PORTG, 0x00),
  //  IS(SPMCSR, 0x00),
  IS(EICRA, 0x00),
  IS(XMCRB, 0x00),
  IS(XMCRA, 0x00),
  //  IS(OSCCAL, 0x00),

  IS(TWBR, 0x00),
  IS(TWSR, 0x00),
  IS(TWAR, 0xFE), // 0xFE
  //  IS(TWDR, 0x00),
  IS(TWCR, 0x00),
  IS(OCR1CL, 0x00),
  IS(OCR1CH, 0x00),
  IS(TCCR1C, 0x00),
  IS(ETIFR, 0x3F), // 0x3F
  IS(ETIMSK, 0x00),
  IS(ICR3L, 0x00),
  IS(ICR3H, 0x00),
  IS(OCR3CL, 0x00),
  IS(OCR3CH, 0x00),
  IS(OCR3BL, 0x00),
  IS(OCR3BH, 0x00),
  IS(OCR3AL, 0x00),
  IS(OCR3AH, 0x00),
  IS(TCNT3L, 0x00),
  IS(TCNT3H, 0x00),
  IS(TCCR3B, 0x00),
  IS(TCCR3A, 0x00),
  IS(TCCR3C, 0x00),
  IS(UCSR0C, 0x06), // 0x06
  IS(UBRR1H, 0x00),
  IS(UBRR1L, 0x00),
  IS(UCSR1B, 0x00),
  IS(UCSR1A, 0x00),
  //  IS(UDR1, 0x00),
  IS(UCSR1C, 0x06), // 0x06

  {VOID_UNDEF, 0x00}
};