[avr-gcc-list] Slight error in GCC instruction patterns

[Andy H]

I'm posting this since I'll forget about it before I'll have time to 
post bug or patch in 2 weeks or so.

I found bug/missed optimization in byte move patterns.

Specfically, we miss the case than a load of zero to any register is as 
cheap as register to register move. Also that Q constrain memory is 
cheaper than regular memory.
Better patterns should appear early in constraints, as this is used by 
register allocator to determine best class of register to use.

Oddly 16 and 32 bit moves have got this correct.

One effect is that we can end up requiring a  register R16-R31 with a 
zero to clear a memory location or  stack slot. Whereas any register 
will do.

Here is what should be used the "L" and "Q" are new.

(define_insn "*movqi"
 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,d,Qm,r,q,r,*r")
   (match_operand:QI 1 "general_operand"       "rL,i,rL,Qm,r,q,i"))]


Andy