binutils and G5/ppc970

[Chris Friesen]

The 970 has a new instruction, called "dcbzl".  It is exactly like "dcbz", except that it operations 
on 128-byte cachelines unconditionally, while "dcbz" operates on 32/128 byte cachelines depending on 
a particular processor-specific bit.

The "dcbzl" instruction is distinguished from "dcbz" by the fact that the 10th bit (in IBM's 
nomenclature where the high order bit is bit zero) is set.

ie:

dcbz  0x7c0007ec
dcbzi 0x7c2007ec

I don't know enough about binutils to actually submit the proper patch.

Chris