Re: PA-RISC bug in gas

[Dan Bonachea]

At 02:50 AM 5/18/2005, Nick Clifton wrote:
> Hi Dan,
>
> > Hi - I'm trying to use gas 2.15 on PA-RISC, and I want to issue an ldcws 
> > instruction like:
> >     ldcws,co 0(%r20), %r19
> > which is accepted by the HP assembler, but gas barfs with:
> >    Error: Invalid Short Load/Store Completer.
> > gas apparently doesn't like the cache control hint completor, which is 
> > critical for semaphore performance on PA-RISC. I've tried every reasonable 
> > combination of characters for the completer that I can think of, and nothing 
> > seems to work.
>
> I passed this question and your proposed patch onto the HPPA binutils port 
> maintainer.  This is what he had to say about it:
>
> : One problem is you are mixing PA 1.x and 2.0 assembler semantics.
> : The co completer is a PA 2.0 feature.  PA 1.x processors don't
> : support this completer.  The PA 2.0 semantics is ldcw,co.  I guess
> : the HP assembler accepts ldcws as a synonym for ldcw when generating
> : PA 2.0 code.
>
> : I suspect that if Dan changes ldcws to ldcw and specifies .level
> : correctly, the assembler will accept the co completer.
>
> I hope that this helps.

With all due respect, I believe your unnamed maintainer may have it backwards. 
According to the "PA-RISC 1.1 Architecture and Instruction Set Reference 
Manual, February 1994" page 5-18 Table 5.10, the CO completer *is* supported 
in the PA-RISC 1.1 ABI (although it's just a hint, so the processor 
implementation is of course free to ignore it). On the contrary, "ldcw" does 
not appear to be a valid PA 1.1 instruction - it does not appear anywhere in 
the architecture manual, although both gas and the HP assembler accept it and 
generate the same opcode as ldcws (must be an alias for the same 
instruction?). Here is some assembly output from the HP assembler:

   12 0000000C (0F0015DC)          ldcws,co (%arg2),%ret0
   13 00000010 (0F0015DC)          ldcw,co (%arg2),%ret0
   14 00000014 (0F0011DC)          ldcws (%arg2),%ret0
   15 00000018 (0F0011DC)          ldcw (%arg2),%ret0
Note that all four mnemonics generate the same opcode, the only difference 
being the

In any case, it seems the HP assembler is correct to accept ldcws,co - the HP 
document "Implementing Spinlocks on the Intel Itanium Architecture and 
PA-RISC, 2003" includes the assembly code below, which notably includes a use 
of ldcws,co and works on the HP assembler.

I've verified that gas does indeed accept "ldcw,co", but this doesn't make 
sense because it rejects "ldcws,co" which seems to be the exact same 
instruction as far as the ABI is concerned.

Dan

.code
.export load_and_clear,entry,priv_lev=3,rtnval=gr
.proc

load_and_clear
        .callinfo no_calls
        .enter
        addi 15,%arg0,%arg2
        depi 0,31,4,%arg2
        bv (%r2)
        ldcws,co (%arg2),%ret0
.leave
.procend