[Bug ld/23244] RISC-V 64 relocation truncated to fit in case of undefined weak references

[wilson at tuliptree dot org]

https://sourceware.org/bugzilla/show_bug.cgi?id=23244

--- Comment #5 from Jim Wilson <wilson at tuliptree dot org> ---
On Thu, 2018-05-31 at 09:22 +0000, palmer at gcc dot gnu.org wrote:
> A similar technique might be possible for R_RISCV_CALL, we could
> convert it to
> an internal R_RISCV_CALL_ABS relocation and then generate a lui-based 
> sequence.

For jalr we can just use x0 for zero-based addressing.  I have an
untested prototype patch that modifies the jalr instruction to use x0
and sets the relocation value to the auipc address, so the offset comes
out as zero.  I don't touch the auipc.  This is just 13 lines of code. 

An R_RISCV_CALL_ABS relocation might be cleaner, but may end up as a
larger patch, and we don't need the generality as we only need support
for a single value, 0.  Zero-page addressing is already handled by
relaxation, it is only weak undef 0 that we need to handle here.

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