Re: bug in avr-as [redux] ?

[rm]

ok,  sorry for the repeat.  initially i thought that the names not
being fixed up were a symptom of the problem i was having, but after
having been disabused of that notion here is the real issue (i think,
feel free to point out where i screwed up).

basically, if i compile to ihex, and to elf, and then do a diff of the
objdumps of each; the ihex version has an opcode incorrect.

the diff file:

2c2
< accel-ava.hex:     file format ihex
---
> a.out:     file format elf32-avr
4c4
< Disassembly of section .sec1:
---
> Disassembly of section .text:
6c6
< 00000000 <.sec1>:
---
> 00000000 <main-0x1c>:
20a21,22
> 
> 0000001c <main>:
51a54,55
> 
> 0000005a <loop>:
52a57,58
> 
> 0000005c <irq_0_callback>:
66c72
<   76: 62 e1           ldi     r22, 0x12       ; 18
---
>   76: e2 e8           ldi     r30, 0x82       ; 130
71a78,79
> 
> 00000082 <jmptbl0>:
76a85,86
> 
> 0000008c <irq0_s0>:
77a88,89
> 
> 0000008e <irq0_s1>:
78a91,92
> 
> 00000090 <irq0_s2>:
79a94,95
> 
> 00000092 <irq0_s3>:
80a97,98
> 
> 00000094 <irq0_s4>:
82a101,102
> 
> 00000098 <irq_1_callback>:
96a117
> Disassembly of section .data:
-----------------------------------------------------

the make file to compare stuff:

all: 
        rm -rf accel-ava.hex
        avr-cpp accel-ava.s accel-ava.cpp.s
        avr-as -o accel-ava.cpp.o accel-ava.cpp.s
        avr-ld --oformat ihex -o accel-ava.hex accel-ava.cpp.o
        avr-ld accel-ava.cpp.o

        avr-objdump -mavr -Dr accel-ava.hex > file1
        avr-objdump -mavr -Dr a.out > file2
        diff file1 file2 > elfihex.diff

---------------------------------------------------------
the source: (io44333.h comes with the bin util distribution, or gcc)

#include "io4433.h"

/* r16 is int 0's temp reg and r17 is int 1's
 *
 */

        
/* the following hold what state of the cycle we are on
 *      ie. looking for rising edge, or time to calculate and
 *     make result available etc
 */
#define IRQ0_STATE_REG    r20
#define IRQ1_STATE_REG    r21

.macro mask_int0
        in    r16, GIMSK
        andi  r16, 0xBF 
        out   GIMSK, r16
.endm

.macro unmask_int0
        in    r16, GIMSK
        ori   r16, 0x40 
        out   GIMSK, r16
.endm


.macro mask_int1
        in    r17, GIMSK   
        andi  r17, 0x7F    
        out   GIMSK, r17
.endm


.macro  unmask_int1
        in    r17, GIMSK
        ori   r17, 0x80 
        out   GIMSK, r17
.endm

.macro  toggle_int0_edge_sensitivity
        in  r16, MCUCR 
        ldi r18, 1     
        eor r16, r18   
        out MCUCR, r16 
.endm

.macro toggle_int1_edge_sensitivity
        in  r17, MCUCR          
        ldi r19, 4              
        eor r17, r19            
        out MCUCR,r17           
.endm
        

.macro set_int0_rising_edge
        in  r16, MCUCR        
        ori r16, 3              
        out MCUCR, r16          
.endm

.macro set_int1_rising_edge
        in  r17, MCUCR          
        ori r17, 0x0C           
        out MCUCR,r17
.endm
                

        .org 0x00
        
        rjmp main    /* 1. reset, ext pin, power-on, brown-out, watchdog */
        rjmp irq_0_callback     /* 2. external interrupt 0 */
        rjmp irq_1_callback     /* 3. external interrupt 1 */
        reti           /* 4. timer 1 capture event */
        reti           /* 5. timer 1 compare match */
        reti           /* 6. timer 1 overflow     */
        reti           /* 7. timer 0 overflow    */ 
        reti           /* 8. serial transfer complete    */
        reti           /* 9. uart rx complete            */
        reti           /*10. uart data register empty    */
        reti           /*11. uart tx complete            */
        reti           /*12. adc conversion complete     */
        reti           /*13. eeprom ready                */
        reti           /*14. analog comparator           */
                
        
main:
        /* int 0 and int 1 are pins PD2 PD3, on 32 and 1 
         * DDRD should then have 0's for input 
         * or 1111 0011 = 0xf3
         */
        ldi     r16, 0xff 
        out     DDRB, r16
        out     DDRC, r16   /* use all pins on PortC for output */

        ldi     r16, 0x00
        out     PORTD, r16  /* make sure no pullups are used on the inputs */
        ldi     r16, 0xf3
        out     DDRD, r16   /* int 0, int 1 as input */

        set_int0_rising_edge
        set_int1_rising_edge    

        /* get the clock ready */
        ldi     r16, 0x00  
        out     TCNT1H, r16  /* reset TCNT1 */
        out     TCNT1L, r16
        ldi     r16, 0x00
        out     TCCR1A, r16   /* no output to pin, no pwm */
        ldi     r16, 0x02
        out     TCCR1B, r16   /* CLK/8 prescaler */

        // clear the state registers
        eor     IRQ0_STATE_REG, IRQ0_STATE_REG
        eor     IRQ1_STATE_REG, IRQ1_STATE_REG
        

        // clear external interrupts before we turn them on
        ldi     r16, 0x00
        out     GIFR, r16
        // setup the external interrupts
        unmask_int0
        unmask_int1
        sei                   /* enable interrupts*/
loop:   
        rjmp    loop    




irq_0_callback: 
        mask_int0
        toggle_int0_edge_sensitivity
        unmask_int0
        /*  low byte should be read first of the timer   */
        in      r3, TCNT1L
        in      r4, TCNT1H
        inc     IRQ0_STATE_REG

        ldi     r30, lo8(jmptbl0)
        ldi     r31, hi8(jmptbl0)
        // now we add the offset to the Z register lo byte and hope
        // it doesn't cross a 256 byte boundry :D
        // multiply the inc by two by shifting since, instructions are 16
        // bit
        mov     r29, IRQ0_STATE_REG
        lsl     r29
        add     r30, r29
        ijmp

jmptbl0:        
        rjmp    irq0_s0
        rjmp    irq0_s1
        rjmp    irq0_s2
        rjmp    irq0_s3
        rjmp    irq0_s4

irq0_s0:
        reti
irq0_s1:
        reti
irq0_s2:
        reti
irq0_s3:
        reti
irq0_s4:
        eor     IRQ0_STATE_REG, IRQ0_STATE_REG  
        reti


irq_1_callback: 
        mask_int1
        toggle_int1_edge_sensitivity
        unmask_int1
        /* low byte should be read first of the timer */
        in      r1, TCNT1L
        in      r2, TCNT1H
        inc     IRQ1_STATE_REG
        reti

.end



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----
Robert Melby
Georgia Institute of Technology, Atlanta Georgia, 30332
uucp:     ...!{decvax,hplabs,ncar,purdue,rutgers}!gatech!prism!gt4255a
Internet: address@hidden