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Re: SMP, barriers, etc.

From: Da Zheng
Subject: Re: SMP, barriers, etc.
Date: Mon, 28 Dec 2009 10:31:26 +0800
User-agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.5; en-US; rv: Gecko/20091204 Thunderbird/3.0

On 09-12-27 下午6:38, Samuel Thibault wrote:
> Da Zheng, le Sun 27 Dec 2009 16:39:04 +0800, a écrit :
>> Is the process above correct?
> I have never actually programmed the architectures where things work
> like this (powerpc & such), but that's what I have understood from the
> code and explanations here and there, yes.  It's a sort of transactional
> memory actually.
I just think if it's a bit too expensive that a processor has to monitor other
processors' cache even though it's only one address. But it should be much less
expensive than Intel's approach.

That conditional store instruction needs to do more if it succeeds. It has to
invalidate cache lines specified by the monitored address in other processors.

Now it seems to me that the memory barrier is only to ensure that the processor
executes instructions in the order we want. But the data dependency barrier
seems to imply cache coherency according to
linux/Documentation/memory-barriers.txt. A bit confused:-(

Zheng Da

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