From reading
through the current bug list, it would appear as though this
behavior
is
manifested as a result of make's current variable
instantiation algorithm, which
instantiates all variables at the beginning of a
rule.
With
this limitation in place, it is impossible to 'make' a Makefile from
rules
which
may analyze the makefile under construction, as
follows:
include targets.d
targets.d : Makefile
$(call
create-rule-to-append-targets-file)
$(call
create-rule-to-analyze-and-append-targets-file) # fails, because
# shell commands used to interpret the targets.d file
contents are executed
# before the targets.d
file is created.
I
would advocate for the one of the
following fixes:
- expansion of variables to occur at the start of
each line of execution, performance
permitting, or,
- the
inclusion of a $(reexpand var) function which would reinstantiate a
variable and
return its new contents upon request.
Regards,
Matt
Hastie.
---------------------------------------------------------------
Senior Software Engineer
Astracon Inc
6560 South Greenwood Plaza Blvd, Suite 200
Englewood, Colorado, 80111
email: address@hidden
phone:
+1-720-895-8547
---------------------------------------------------------------