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Re: Static pattern usage

From: Sam Ravnborg
Subject: Re: Static pattern usage
Date: Fri, 3 Oct 2003 23:44:11 +0200
User-agent: Mutt/1.4.1i

On Fri, Oct 03, 2003 at 05:26:54PM -0400, Paul D. Smith wrote:
> No make expands $* in the prerequisites list to the name of the target.


foo.o : _$* FORCE
        echo $^


I expected make to print out:
make: *** No rule to make target `_foo.o', needed by `foo.o'.  Stop.

But I got:
make: *** No rule to make target `_', needed by `foo.o'.  Stop.

That seems to me that make does not expand $* to the target.
See also the manual:

Section: Missing:
* In some Unix `make's, the automatic variable `$*' appearing in the
     prerequisites of a rule has the amazingly strange "feature" of
     expanding to the full name of the _target of that rule_.  We cannot
     imagine what went on in the minds of Unix `make' developers to do
     this; it is utterly inconsistent with the normal definition of

And it does not seem to happen in the above example.

> The only way to do what you want is to use the $(eval ...) function to
> declare extra dependencies.  Something like:
>   OBJS = foo.o
>   deps_foo.o := foo.h
>   $(foreach target,$(OBJS),$(eval $(target): $$(deps_$(target))))

Not an option for me - I have to support 3.79.1.

Thanks for feedback.


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