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[Commit-gnuradio] r3525 - usrp-hw/trunk/sym/generated
|
From: |
matt |
|
Subject: |
[Commit-gnuradio] r3525 - usrp-hw/trunk/sym/generated |
|
Date: |
Mon, 11 Sep 2006 17:30:13 -0600 (MDT) |
Author: matt
Date: 2006-09-11 17:30:13 -0600 (Mon, 11 Sep 2006)
New Revision: 3525
Added:
usrp-hw/trunk/sym/generated/Makefile
usrp-hw/trunk/sym/generated/README
usrp-hw/trunk/sym/generated/xc3sXX00fg456-CFG.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-CLK.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO0.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO1.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO2.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO3.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO4.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO5.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO6.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO7.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-JTAG.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-PWR.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-VREF.src
Removed:
usrp-hw/trunk/sym/generated/make_symbols
Modified:
usrp-hw/trunk/sym/generated/xilinxgen
Log:
xilinx files, which are mostly generated by xilinxgen
Makefile thanks to jcorgan
Added: usrp-hw/trunk/sym/generated/Makefile
===================================================================
--- usrp-hw/trunk/sym/generated/Makefile (rev 0)
+++ usrp-hw/trunk/sym/generated/Makefile 2006-09-11 23:30:13 UTC (rev
3525)
@@ -0,0 +1,137 @@
+#!/usr/bin/make
+
+TRAGESYM=/usr/bin/tragesym
+
+SOURCES=ad813x.sym \
+ ad8347-BIAS.sym \
+ ad8347-MIX.sym \
+ ad8347-OUT.sym \
+ ad8347-PWR.sym \
+ ad8348-BIAS.sym \
+ ad8348-MIX.sym \
+ ad8348-OUT.sym \
+ ad8348-PWR.sym \
+ ad834X-MIX.sym \
+ ad834X-PWR.sym \
+ ad9238-A.sym \
+ ad9238-B.sym \
+ ad9238-CTRL.sym \
+ ad9238-PWR.sym \
+ ad9510-CTRL.sym \
+ ad9510-OUTA.sym \
+ ad9510-OUTB.sym \
+ ad9510-PLL.sym \
+ ad9510-PWR.sym \
+ ad9513-CLK.sym \
+ ad9513-CTRL.sym \
+ ad9513-PWR.sym \
+ ad9767-CH1.sym \
+ ad9767-CH2.sym \
+ ad9767-CTRL.sym \
+ ad9767-PWR.sym \
+ ad9777-CH1.sym \
+ ad9777-CH2.sym \
+ ad9777-CTRL.sym \
+ ad9777-PWR.sym \
+ ad986X-ACTRL.sym \
+ ad986X-AUX.sym \
+ ad986X-CLK.sym \
+ ad986X-CTRL.sym \
+ ad986X-PWR.sym \
+ ad986X-RX.sym \
+ ad986X-TX.sym \
+ adf4360-ANLG.sym \
+ adf4360-DIG.sym \
+ adf4360-PWR.sym \
+ adp3336.sym \
+ bs2s7hz1204.sym \
+ cy7c68013-tq100-BUS.sym \
+ cy7c68013-tq100-CTRL.sym \
+ cy7c68013-tq100-MISC.sym \
+ cy7c68013-tq100-PA.sym \
+ cy7c68013-tq100-PC.sym \
+ cy7c68013-tq100-PE.sym \
+ cy7c68013-tq100-PWR.sym \
+ ep1c12-pq240-CFG.sym \
+ ep1c12-pq240-CLKA.sym \
+ ep1c12-pq240-CLKB.sym \
+ ep1c12-pq240-IO1.sym \
+ ep1c12-pq240-IO2.sym \
+ ep1c12-pq240-IO3.sym \
+ ep1c12-pq240-IO4.sym \
+ ep1c12-pq240-JTAG.sym \
+ ep1c12-pq240-PWR.sym \
+ ep2c20-f484-CFG.sym \
+ ep2c20-f484-IO1.sym \
+ ep2c20-f484-IO2.sym \
+ ep2c20-f484-IO3.sym \
+ ep2c20-f484-IO4.sym \
+ ep2c20-f484-IO5.sym \
+ ep2c20-f484-IO6.sym \
+ ep2c20-f484-IO7.sym \
+ ep2c20-f484-IO8.sym \
+ ep2c20-f484-JTAG.sym \
+ ep2c20-f484-NC.sym \
+ ep2c20-f484-PWR.sym \
+ hmc174ms8.sym \
+ hws383.sym \
+ irm046u-HB.sym \
+ irm046u-LB.sym \
+ irm046u-PWR.sym \
+ lm2940imp.sym \
+ lt1085.sym \
+ lt1767.sym \
+ lt3462.sym \
+ ltc2284-A.sym \
+ ltc2284-B.sym \
+ ltc2284-CTRL.sym \
+ ltc2284-PWR.sym \
+ max128X.sym \
+ max211x-DIG.sym \
+ max211x-PLL.sym \
+ max211x-PWR.sym \
+ max211x-SIG.sym \
+ max282X-CTRL.sym \
+ max282X-PWR.sym \
+ max282X-RX.sym \
+ max282X-TX.sym \
+ max355x-BIAS.sym \
+ max355x-DIG.sym \
+ max355x-IF.sym \
+ max355x-PLL.sym \
+ max355x-PWR.sym \
+ max355x-RF.sym \
+ max502x.sym \
+ max5742.sym \
+ mic5216.sym \
+ mt4736py5.sym \
+ mt4937di5.sym \
+ saw.sym \
+ template.sym \
+ tps777xx-pwp.sym \
+ va1t1ur2076.sym \
+ vctcxo-diff.sym \
+ vctcxo.sym \
+ xc3sXX00fg456-IO0.sym \
+ xc3sXX00fg456-IO1.sym \
+ xc3sXX00fg456-IO2.sym \
+ xc3sXX00fg456-IO3.sym \
+ xc3sXX00fg456-IO4.sym \
+ xc3sXX00fg456-IO5.sym \
+ xc3sXX00fg456-IO6.sym \
+ xc3sXX00fg456-IO7.sym \
+ xc3sXX00fg456-CFG.sym \
+ xc3sXX00fg456-CLK.sym \
+ xc3sXX00fg456-PWR.sym \
+ xc3sXX00fg456-JTAG.sym \
+ xc3sXX00fg456-VREF.sym
+
+
+all : $(SOURCES)
+
+clean :
+ @rm -f *.sym
+
+%.sym : %.src
+ $(TRAGESYM) $< $@
+
Added: usrp-hw/trunk/sym/generated/README
===================================================================
--- usrp-hw/trunk/sym/generated/README (rev 0)
+++ usrp-hw/trunk/sym/generated/README 2006-09-11 23:30:13 UTC (rev 3525)
@@ -0,0 +1 @@
+Run make to create the symbol files
Deleted: usrp-hw/trunk/sym/generated/make_symbols
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg456-CFG.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-CFG.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-CFG.src 2006-09-11 23:30:13 UTC
(rev 3525)
@@ -0,0 +1,39 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG456-CFG
+device=XC3SXX00FG456
+refdes=U?
+footprint=FG456
+description=Xilinx Spartan 3 400/1000/1500/2000 FG456
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A2 io line l PROG\_B
+B3 io line l HSWAP\_EN
+U12 io line r IO\_L30N\_4/D2
+V11 io line r IO\_L31P\_5/D5
+V12 io line r IO\_L30P\_4/D3
+W11 io line r IO\_L31N\_5/D4
+W12 io line r IO\_L31N\_4/INIT\_B
+Y4 io line r IO\_L01N\_5/RDWR\_B
+Y12 io line r IO\_L31P\_4/DOUT/BUSY
+AA1 io line l M1
+AA3 io line r IO\_L01P\_5/CS\_B
+AA9 io line r IO\_L28P\_5/D7
+AA14 io line r IO\_L27N\_4/DIN/D0
+AA22 io line l CCLK
+AB2 io line l M0
+AB3 io line l M2
+AB9 io line r IO\_L28N\_5/D6
+AB14 io line r IO\_L27P\_4/D1
+AB21 io line l DONE
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg456-CLK.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-CLK.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-CLK.src 2006-09-11 23:30:13 UTC
(rev 3525)
@@ -0,0 +1,28 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG456-CLK
+device=XC3SXX00FG456
+refdes=U?
+footprint=FG456
+description=Xilinx Spartan 3 400/1000/1500/2000 FG456
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A11 clk clk l IO\_L32P\_0/GCLK6
+B11 clk clk l IO\_L32N\_0/GCLK7
+B12 clk clk l IO\_L32N\_1/GCLK5
+C12 clk clk l IO\_L32P\_1/GCLK4
+Y11 clk clk l IO\_L32P\_5/GCLK2
+AA11 clk clk l IO\_L32N\_5/GCLK3
+AA12 clk clk l IO\_L32N\_4/GCLK1
+AB12 clk clk l IO\_L32P\_4/GCLK0
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO0.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO0.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO0.src 2006-09-11 23:30:13 UTC
(rev 3525)
@@ -0,0 +1,53 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG456-IO0
+device=XC3SXX00FG456
+refdes=U?
+footprint=FG456
+description=Xilinx Spartan 3 400/1000/1500/2000 FG456
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A4 io line l IO\_L01P\_0/VRN\_0/DCI
+A5 io line l IO\_L09P\_0
+A7 io line r IO\_L19P\_0/400NC
+A8 io line l IO\_L24P\_0
+A9 io line l IO\_L27P\_0
+A10 io line l IO
+B4 io line l IO\_L01N\_0/VRP\_0/DCI
+B5 io line l IO\_L09N\_0
+B6 io line l IO\_L15P\_0
+B7 io line r IO\_L19N\_0/400NC
+B8 io line l IO\_L24N\_0
+B9 io line l IO\_L27N\_0
+B10 io line l IO\_L29P\_0
+C5 io line l IO\_L06P\_0
+C6 io line l IO\_L15N\_0
+C10 io line l IO\_L29N\_0
+D5 io line l IO\_L06N\_0
+D6 io line l IO\_L10P\_0
+D7 io line l IO\_L16P\_0
+D8 io line r IO\_L22P\_0/400NC
+D9 io line l IO
+D10 io line l IO
+D11 io line l IO\_L31N\_0
+E6 io line l IO\_L10N\_0
+E7 io line l IO\_L16N\_0
+E8 io line r IO\_L22N\_0/400NC
+E9 io line l IO\_L25P\_0
+E10 io line l IO\_L28P\_0
+E11 io line l IO\_L30P\_0
+F6 io line l IO
+F9 io line l IO\_L25N\_0
+F10 io line l IO\_L28N\_0
+F11 io line l IO\_L30N\_0
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO1.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO1.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO1.src 2006-09-11 23:30:13 UTC
(rev 3525)
@@ -0,0 +1,53 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG456-IO1
+device=XC3SXX00FG456
+refdes=U?
+footprint=FG456
+description=Xilinx Spartan 3 400/1000/1500/2000 FG456
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A12 io line l IO
+A13 io line l IO\_L30N\_1
+A14 io line l IO\_L28N\_1
+A15 io line l IO\_L25P\_1
+A16 io line r IO\_L22N\_1/400NC
+B13 io line l IO\_L30P\_1
+B14 io line l IO\_L28P\_1
+B15 io line l IO\_L25N\_1
+B16 io line r IO\_L22P\_1/400NC
+B17 io line l IO\_L16N\_1
+B18 io line l IO\_L10P\_1
+B19 io line l IO\_L06P\_1
+B20 io line l IO\_L01P\_1/VRN\_1/DCI
+C13 io line l IO\_L29N\_1
+C16 io line r IO\_L19N\_1/400NC
+C17 io line l IO\_L16P\_1
+C18 io line l IO\_L09N\_1
+C19 io line l IO\_L01N\_1/VRP\_1/DCI
+D13 io line l IO\_L29P\_1
+D14 io line l IO\_L27N\_1
+D15 io line l IO\_L24N\_1
+D16 io line r IO\_L19P\_1/400NC
+D17 io line l IO\_L15N\_1
+D18 io line l IO\_L09P\_1
+E12 io line l IO\_L31P\_1
+E14 io line l IO\_L27P\_1
+E15 io line l IO\_L24P\_1
+E16 io line l IO
+E17 io line l IO\_L15P\_1
+F12 io line l IO
+F13 io line l IO
+F16 io line l IO
+F17 io line l IO
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO2.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO2.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO2.src 2006-09-11 23:30:13 UTC
(rev 3525)
@@ -0,0 +1,59 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG456-IO2
+device=XC3SXX00FG456
+refdes=U?
+footprint=FG456
+description=Xilinx Spartan 3 400/1000/1500/2000 FG456
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+C20 io line l IO\_L01N\_2/VRP\_2/DCI
+C21 io line l IO\_L01P\_2/VRN\_2/DCI
+C22 io line l IO
+D19 io line l IO\_L16P\_2
+D20 io line l IO\_L16N\_2
+D21 io line l IO\_L17N\_2
+E18 io line l IO\_L19N\_2
+E19 io line l IO\_L20N\_2
+E20 io line l IO\_L20P\_2
+E21 io line l IO\_L21N\_2
+E22 io line l IO\_L21P\_2
+F18 io line l IO\_L19P\_2
+F20 io line l IO\_L24N\_2
+F21 io line l IO\_L24P\_2
+G17 io line l IO\_L22N\_2
+G18 io line l IO\_L22P\_2
+G19 io line l IO\_L23P\_2
+G20 io line r IO\_L26N\_2/400NC
+G21 io line l IO\_L27N\_2
+G22 io line l IO\_L27P\_2
+H18 io line r IO\_L28N\_2/400NC
+H19 io line r IO\_L26P\_2/400NC
+H21 io line r IO\_L29N\_2/400NC
+H22 io line r IO\_L29P\_2/400NC
+J17 io line r IO\_L28P\_2/400NC
+J18 io line r IO\_L31N\_2/400NC
+J19 io line r IO\_L31P\_2/400NC
+J21 io line r IO\_L32N\_2/400NC
+J22 io line r IO\_L32P\_2/400NC
+K17 io line r IO\_L33N\_2/400NC
+K18 io line r IO\_L33P\_2/400NC
+K20 io line l IO\_L34P\_2
+K21 io line l IO\_L35N\_2
+K22 io line l IO\_L35P\_2
+L17 io line l IO\_L38N\_2
+L18 io line l IO\_L38P\_2
+L19 io line l IO\_L39N\_2
+L20 io line l IO\_L39P\_2
+L21 io line l IO\_L40N\_2
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO3.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO3.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO3.src 2006-09-11 23:30:13 UTC
(rev 3525)
@@ -0,0 +1,59 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG456-IO3
+device=XC3SXX00FG456
+refdes=U?
+footprint=FG456
+description=Xilinx Spartan 3 400/1000/1500/2000 FG456
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+M17 io line l IO\_L38P\_3
+M18 io line l IO\_L38N\_3
+M19 io line l IO\_L39P\_3
+M20 io line l IO\_L39N\_3
+M21 io line l IO\_L40P\_3
+N17 io line r IO\_L33P\_3/400NC
+N18 io line r IO\_L33N\_3/400NC
+N20 io line l IO\_L34N\_3
+N21 io line l IO\_L35P\_3
+N22 io line l IO\_L35N\_3
+P17 io line r IO\_L31P\_3/400NC
+P18 io line r IO\_L31N\_3/400NC
+P19 io line r IO\_L29N\_3/400NC
+P21 io line r IO\_L32P\_3/400NC
+P22 io line r IO\_L32N\_3/400NC
+R18 io line l IO\_L24N\_3
+R19 io line r IO\_L29P\_3/400NC
+R21 io line r IO\_L28P\_3/400NC
+R22 io line r IO\_L28N\_3/400NC
+T17 io line l IO\_L22N\_3
+T18 io line l IO\_L24P\_3
+T19 io line r IO\_L26P\_3/400NC
+T20 io line r IO\_L26N\_3/400NC
+T21 io line l IO\_L27P\_3
+T22 io line l IO\_L27N\_3
+U18 io line l IO\_L22P\_3
+U19 io line l IO\_L20N\_3
+U21 io line l IO\_L23N\_3
+V19 io line l IO\_L17N\_3
+V20 io line l IO\_L20P\_3
+V21 io line l IO\_L21P\_3
+V22 io line l IO\_L21N\_3
+W20 io line l IO\_L19P\_3
+W21 io line l IO\_L19N\_3
+W22 io line l IO\_L16N\_3
+Y19 io line l IO\_L01P\_3/VRN\_3/DCI
+Y20 io line l IO\_L01N\_3/VRP\_3/DCI
+Y21 io line l IO
+Y22 io line l IO\_L16P\_3
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO4.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO4.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO4.src 2006-09-11 23:30:13 UTC
(rev 3525)
@@ -0,0 +1,48 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG456-IO4
+device=XC3SXX00FG456
+refdes=U?
+footprint=FG456
+description=Xilinx Spartan 3 400/1000/1500/2000 FG456
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+U13 io line l IO\_L28N\_4
+U14 io line l IO\_L25N\_4
+U16 io line l IO
+U17 io line l IO
+V13 io line l IO\_L28P\_4
+V14 io line l IO\_L25P\_4
+V16 io line l IO\_L16N\_4
+V17 io line l IO\_L10N\_4
+W13 io line l IO
+W14 io line l IO
+W15 io line r IO\_L22P\_4/400NC
+W16 io line l IO\_L16P\_4
+W17 io line l IO\_L10P\_4
+Y13 io line l IO\_L29N\_4
+Y17 io line l IO\_L15N\_4
+Y18 io line l IO\_L06P\_4
+AA13 io line l IO\_L29P\_4
+AA15 io line l IO\_L24N\_4
+AA16 io line r IO\_L19N\_4/400NC
+AA17 io line l IO\_L15P\_4
+AA18 io line l IO\_L09N\_4
+AA19 io line r IO\_L05N\_4/400NC
+AA20 io line l IO\_L01N\_4/VRP\_4/DCI
+AB15 io line l IO\_L24P\_4
+AB16 io line r IO\_L19P\_4/400NC
+AB18 io line l IO\_L09P\_4
+AB19 io line r IO\_L05P\_4/400NC
+AB20 io line l IO\_L01P\_4/VRN\_4/DCI
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO5.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO5.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO5.src 2006-09-11 23:30:13 UTC
(rev 3525)
@@ -0,0 +1,47 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG456-IO5
+device=XC3SXX00FG456
+refdes=U?
+footprint=FG456
+description=Xilinx Spartan 3 400/1000/1500/2000 FG456
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+U7 io line l IO
+U9 io line r IO/400NC
+U10 io line l IO
+U11 io line l IO
+V6 io line l IO\_L15P\_5
+V7 io line l IO
+V8 io line l IO\_L24P\_5
+V9 io line l IO\_L27P\_5
+V10 io line l IO
+W5 io line l IO\_L09P\_5
+W6 io line l IO\_L15N\_5
+W8 io line l IO\_L24N\_5
+Y5 io line l IO\_L09N\_5
+Y6 io line l IO\_L16P\_5
+Y7 io line r IO\_L19N\_5/400NC
+Y10 io line l IO\_L29N\_5
+AA4 io line l IO\_L06P\_5
+AA5 io line l IO\_L10P\_5/VRN\_5/DCI
+AA6 io line l IO\_L16N\_5
+AA7 io line r IO\_L22P\_5/400NC
+AA8 io line l IO\_L25P\_5
+AA10 io line l IO\_L30P\_5
+AB4 io line l IO\_L06N\_5
+AB5 io line l IO\_L10N\_5/VRP\_5/DCI
+AB7 io line r IO\_L22N\_5/400NC
+AB8 io line l IO\_L25N\_5
+AB10 io line l IO\_L30N\_5
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO6.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO6.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO6.src 2006-09-11 23:30:13 UTC
(rev 3525)
@@ -0,0 +1,59 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG456-IO6
+device=XC3SXX00FG456
+refdes=U?
+footprint=FG456
+description=Xilinx Spartan 3 400/1000/1500/2000 FG456
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+M2 io line l IO\_L40N\_6
+M3 io line l IO\_L39P\_6
+M4 io line l IO\_L39N\_6
+M5 io line l IO\_L38P\_6
+M6 io line l IO\_L38N\_6
+N1 io line l IO\_L35P\_6
+N2 io line l IO\_L35N\_6
+N3 io line l IO\_L34P\_6
+N5 io line r IO\_L33P\_6/400NC
+N6 io line r IO\_L33N\_6/400NC
+P1 io line r IO\_L32P\_6/400NC
+P2 io line r IO\_L32N\_6/400NC
+P4 io line r IO\_L31P\_6/400NC
+P5 io line r IO\_L31N\_6/400NC
+P6 io line r IO\_L28P\_6/400NC
+R1 io line r IO\_L29P\_6/400NC
+R2 io line r IO\_L29N\_6/400NC
+R4 io line r IO\_L26P\_6/400NC
+R5 io line r IO\_L28N\_6/400NC
+T1 io line l IO\_L27P\_6
+T2 io line l IO\_L27N\_6
+T3 io line r IO\_L26N\_6/400NC
+T4 io line l IO\_L23P\_6
+T5 io line l IO\_L22P\_6
+T6 io line l IO\_L22N\_6
+U2 io line l IO\_L24P\_6
+U4 io line l IO\_L23N\_6
+U5 io line l IO\_L19P\_6
+V1 io line l IO\_L21P\_6
+V2 io line l IO\_L21N\_6
+V3 io line l IO\_L20P\_6
+V4 io line l IO\_L20N\_6
+V5 io line l IO\_L19N\_6
+W2 io line l IO\_L17N\_6
+W3 io line l IO\_L16P\_6
+W4 io line l IO\_L16N\_6
+Y1 io line l IO
+Y2 io line l IO\_L01P\_6/VRN\_6/DCI
+Y3 io line l IO\_L01N\_6/VRP\_6/DCI
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO7.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO7.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO7.src 2006-09-11 23:30:13 UTC
(rev 3525)
@@ -0,0 +1,59 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG456-IO7
+device=XC3SXX00FG456
+refdes=U?
+footprint=FG456
+description=Xilinx Spartan 3 400/1000/1500/2000 FG456
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+C2 io line l IO
+C3 io line l IO\_L01N\_7/VRP\_7/DCI
+C4 io line l IO\_L01P\_7/VRN\_7/DCI
+D1 io line l IO\_L16N\_7
+D2 io line l IO\_L19P\_7
+D4 io line l IO\_L17P\_7
+E1 io line l IO\_L21N\_7
+E2 io line l IO\_L21P\_7
+E3 io line l IO\_L20P\_7
+E4 io line l IO\_L17N\_7
+F2 io line l IO\_L23N\_7
+F3 io line l IO\_L23P\_7
+F4 io line l IO\_L20N\_7
+F5 io line l IO\_L22P\_7
+G1 io line l IO\_L27N\_7
+G3 io line r IO\_L26N\_7/400NC
+G4 io line r IO\_L26P\_7/400NC
+G5 io line l IO\_L24P\_7
+G6 io line l IO\_L22N\_7
+H1 io line r IO\_L28N\_7/400NC
+H2 io line r IO\_L28P\_7/400NC
+H4 io line r IO\_L29P\_7/400NC
+H5 io line l IO\_L24N\_7
+J1 io line r IO\_L32N\_7/400NC
+J2 io line r IO\_L32P\_7/400NC
+J4 io line r IO\_L29N\_7/400NC
+J5 io line r IO\_L31N\_7/400NC
+J6 io line r IO\_L31P\_7/400NC
+K1 io line l IO\_L35N\_7
+K2 io line l IO\_L35P\_7
+K3 io line l IO\_L34N\_7
+K4 io line l IO\_L34P\_7
+K5 io line r IO\_L33N\_7/400NC
+K6 io line r IO\_L33P\_7/400NC
+L2 io line l IO\_L40P\_7
+L3 io line l IO\_L39N\_7
+L4 io line l IO\_L39P\_7
+L5 io line l IO\_L38N\_7
+L6 io line l IO\_L38P\_7
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg456-JTAG.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-JTAG.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-JTAG.src 2006-09-11 23:30:13 UTC
(rev 3525)
@@ -0,0 +1,24 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG456-JTAG
+device=XC3SXX00FG456
+refdes=U?
+footprint=FG456
+description=Xilinx Spartan 3 400/1000/1500/2000 FG456
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A20 io line l TMS
+A21 io line l TCK
+B1 io line l TDI
+B22 io line l TDO
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg456-PWR.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-PWR.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-PWR.src 2006-09-11 23:30:13 UTC
(rev 3525)
@@ -0,0 +1,132 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG456-PWR
+device=XC3SXX00FG456
+refdes=U?
+footprint=FG456
+description=Xilinx Spartan 3 400/1000/1500/2000 FG456
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A1 pwr line r GND
+A6 pwr line l VCCAUX
+A17 pwr line l VCCAUX
+A22 pwr line r GND
+B2 pwr line r GND
+B21 pwr line r GND
+C8 pwr line l VCCO\_0
+C9 pwr line r GND
+C14 pwr line r GND
+C15 pwr line l VCCO\_1
+F1 pwr line l VCCAUX
+F8 pwr line l VCCO\_0
+F15 pwr line l VCCO\_1
+F22 pwr line l VCCAUX
+G7 pwr line l VCCINT
+G8 pwr line l VCCINT
+G9 pwr line l VCCO\_0
+G10 pwr line l VCCO\_0
+G11 pwr line l VCCO\_0
+G12 pwr line l VCCO\_1
+G13 pwr line l VCCO\_1
+G14 pwr line l VCCO\_1
+G15 pwr line l VCCINT
+G16 pwr line l VCCINT
+H3 pwr line l VCCO\_7
+H6 pwr line l VCCO\_7
+H7 pwr line l VCCINT
+H16 pwr line l VCCINT
+H17 pwr line l VCCO\_2
+H20 pwr line l VCCO\_2
+J3 pwr line r GND
+J7 pwr line l VCCO\_7
+J9 pwr line r GND
+J10 pwr line r GND
+J11 pwr line r GND
+J12 pwr line r GND
+J13 pwr line r GND
+J14 pwr line r GND
+J16 pwr line l VCCO\_2
+J20 pwr line r GND
+K7 pwr line l VCCO\_7
+K9 pwr line r GND
+K10 pwr line r GND
+K11 pwr line r GND
+K12 pwr line r GND
+K13 pwr line r GND
+K14 pwr line r GND
+K16 pwr line l VCCO\_2
+L7 pwr line l VCCO\_7
+L9 pwr line r GND
+L10 pwr line r GND
+L11 pwr line r GND
+L12 pwr line r GND
+L13 pwr line r GND
+L14 pwr line r GND
+L16 pwr line l VCCO\_2
+M7 pwr line l VCCO\_6
+M9 pwr line r GND
+M10 pwr line r GND
+M11 pwr line r GND
+M12 pwr line r GND
+M13 pwr line r GND
+M14 pwr line r GND
+M16 pwr line l VCCO\_3
+N7 pwr line l VCCO\_6
+N9 pwr line r GND
+N10 pwr line r GND
+N11 pwr line r GND
+N12 pwr line r GND
+N13 pwr line r GND
+N14 pwr line r GND
+N16 pwr line l VCCO\_3
+P3 pwr line r GND
+P7 pwr line l VCCO\_6
+P9 pwr line r GND
+P10 pwr line r GND
+P11 pwr line r GND
+P12 pwr line r GND
+P13 pwr line r GND
+P14 pwr line r GND
+P16 pwr line l VCCO\_3
+P20 pwr line r GND
+R3 pwr line l VCCO\_6
+R6 pwr line l VCCO\_6
+R7 pwr line l VCCINT
+R16 pwr line l VCCINT
+R17 pwr line l VCCO\_3
+R20 pwr line l VCCO\_3
+T7 pwr line l VCCINT
+T8 pwr line l VCCINT
+T9 pwr line l VCCO\_5
+T10 pwr line l VCCO\_5
+T11 pwr line l VCCO\_5
+T12 pwr line l VCCO\_4
+T13 pwr line l VCCO\_4
+T14 pwr line l VCCO\_4
+T15 pwr line l VCCINT
+T16 pwr line l VCCINT
+U1 pwr line l VCCAUX
+U8 pwr line l VCCO\_5
+U15 pwr line l VCCO\_4
+U22 pwr line l VCCAUX
+Y8 pwr line l VCCO\_5
+Y9 pwr line r GND
+Y14 pwr line r GND
+Y15 pwr line l VCCO\_4
+AA2 pwr line r GND
+AA21 pwr line r GND
+AB1 pwr line r GND
+AB6 pwr line l VCCAUX
+AB17 pwr line l VCCAUX
+AB22 pwr line r GND
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg456-VREF.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-VREF.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-VREF.src 2006-09-11 23:30:13 UTC
(rev 3525)
@@ -0,0 +1,56 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG456-VREF
+device=XC3SXX00FG456
+refdes=U?
+footprint=FG456
+description=Xilinx Spartan 3 400/1000/1500/2000 FG456
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A3 io line l IO/VREF\_0
+A18 io line l IO\_L10N\_1/VREF\_1
+A19 io line l IO\_L06N\_1/VREF\_1
+C1 io line l IO\_L16P\_7/VREF\_7
+C7 io line l IO/VREF\_0
+C11 io line l IO\_L31P\_0/VREF\_0
+D3 io line l IO\_L19N\_7/VREF\_7
+D12 io line l IO\_L31N\_1/VREF\_1
+D22 io line l IO\_L17P\_2/VREF\_2
+E5 io line r IO/VREF\_0/400NC
+E13 io line l IO/VREF\_1
+F7 io line l IO/VREF\_0
+F14 io line r IO/VREF\_1/400NC
+F19 io line l IO\_L23N\_2/VREF\_2
+G2 io line l IO\_L27P\_7/VREF\_7
+K19 io line l IO\_L34N\_2/VREF\_2
+L1 io line l IO\_L40N\_7/VREF\_7
+L22 io line l IO\_L40P\_2/VREF\_2
+M1 io line l IO\_L40P\_6/VREF\_6
+M22 io line l IO\_L40N\_3/VREF\_3
+N4 io line l IO\_L34N\_6/VREF\_6
+N19 io line l IO\_L34P\_3/VREF\_3
+U3 io line l IO\_L24N\_6/VREF\_6
+U6 io line l IO/VREF\_5
+U20 io line l IO\_L23P\_3/VREF\_3
+V15 io line r IO\_L22N\_4/VREF\_4/400NC
+V18 io line l IO/VREF\_4
+W1 io line l IO\_L17P\_6/VREF\_6
+W7 io line r IO\_L19P\_5/VREF\_5/400NC
+W9 io line l IO\_L27N\_5/VREF\_5
+W10 io line l IO\_L29P\_5/VREF\_5
+W18 io line l IO\_L06N\_4/VREF\_4
+W19 io line l IO\_L17P\_3/VREF\_3
+Y16 io line l IO/VREF\_4
+AB11 io line l IO/VREF\_5
+AB13 io line l IO/VREF\_4
Modified: usrp-hw/trunk/sym/generated/xilinxgen
===================================================================
--- usrp-hw/trunk/sym/generated/xilinxgen 2006-09-11 21:55:23 UTC (rev
3524)
+++ usrp-hw/trunk/sym/generated/xilinxgen 2006-09-11 23:30:13 UTC (rev
3525)
@@ -31,21 +31,21 @@
[pins]
'''
-configfile = open ('xc3sXX00FG456-CFG.src', 'w')
+configfile = open ('xc3sXX00fg456-CFG.src', 'w')
configfile.write(boilerplate % ("CFG",))
-jtagfile = open ('xc3sXX00FG456-JTAG.src', 'w')
+jtagfile = open ('xc3sXX00fg456-JTAG.src', 'w')
jtagfile.write(boilerplate % ("JTAG",))
-powerfile = open ('xc3sXX00FG456-PWR.src', 'w')
+powerfile = open ('xc3sXX00fg456-PWR.src', 'w')
powerfile.write(boilerplate % ("PWR",))
-clockfile = open ('xc3sXX00FG456-CLK.src', 'w')
+clockfile = open ('xc3sXX00fg456-CLK.src', 'w')
clockfile.write(boilerplate % ("CLK",))
-vreffile = open ('xc3sXX00FG456-VREF.src', 'w')
+vreffile = open ('xc3sXX00fg456-VREF.src', 'w')
vreffile.write(boilerplate % ("VREF",))
iofiles = [0] * 8
for i in range(8):
- iofiles[i] = open ( ('xc3sXX00FG456-IO%d.src' % (i,)), 'w')
+ iofiles[i] = open ( ('xc3sXX00fg456-IO%d.src' % (i,)), 'w')
iofiles[i].write(boilerplate % ('IO%d' % (i,),))
dummy = pinfile.readline()
@@ -71,9 +71,9 @@
elif(pintype == 'VCCAUX'):
writepin(powerfile,elements[3],elements[6],'line','pwr','l')
elif(pintype == 'VCCO'):
- writepin(powerfile,elements[3],elements[6],'line','pwr','t')
+ writepin(powerfile,elements[3],elements[6],'line','pwr','l')
elif(pintype == 'VCCINT'):
- writepin(powerfile,elements[3],elements[6],'line','pwr','b')
+ writepin(powerfile,elements[3],elements[6],'line','pwr','l')
elif(pintype == 'JTAG'):
writepin(jtagfile,elements[3],elements[6],'line','io','l')
@@ -104,19 +104,3 @@
else:
print elements
-
-
-
- #vreffile.write("%s\t\tio\tpwr\tl\t\t%s/400-NC\n" %
(elements[3],elements[6]))
-#iofiles[int(elements[12])].write("%s\t\tio\tline\tl\t\t%s/400-NC\n" %
(elements[3],elements[6]))
-#iofiles[int(elements[12])].write("%s\t\tio\tline\tl\t\t%s\n" %
(elements[3],elements[4]))
- #iofiles[int(elements[12])].write("%s\t\tio\tline\tl\t\t%s/DCI\n" %
(elements[3],elements[4]))
- #vreffile.write("%s\t\tio\tpwr\tl\t\t%s\n" % (elements[3],elements[4]))
- #powerfile.write("%s\t\tpwr\tline\tr\t\t%s\n" %
(elements[3],elements[4]))
- #powerfile.write("%s\t\tpwr\tline\tl\t\t%s\n" %
(elements[3],elements[4]))
- #powerfile.write("%s\t\tpwr\tline\tt\t\t%s\n" %
(elements[3],elements[4]))
- #powerfile.write("%s\t\tpwr\tline\tb\t\t%s\n" %
(elements[3],elements[4]))
- #jtagfile.write("%s\t\tio\tline\tl\t\t%s\n" %
(elements[3],elements[4]))
- #configfile.write("%s\t\tio\tline\tl\t\t%s\n" %
(elements[3],elements[4]))
- #configfile.write("%s\t\tio\tline\tr\t\t%s\n" %
(elements[3],elements[4]))
- #clockfile.write("%s\t\tio\tclk\tl\t\t%s\n" %
(elements[3],elements[4]))
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- [Commit-gnuradio] r3525 - usrp-hw/trunk/sym/generated,
matt <=