[Commit-gnuradio] r4849 - gnuradio/branches/developers/thottelt/tx_usb

[thottelt]

Author: thottelt
Date: 2007-04-02 18:40:46 -0600 (Mon, 02 Apr 2007)
New Revision: 4849

Added:
   gnuradio/branches/developers/thottelt/tx_usb/tx_usb.mpf
   gnuradio/branches/developers/thottelt/tx_usb/usb_fifo_reader.v
   gnuradio/branches/developers/thottelt/tx_usb/usb_fifo_reader_test.v
Removed:
   gnuradio/branches/developers/thottelt/tx_usb/tx_usb.cr.mti
   gnuradio/branches/developers/thottelt/tx_usb/tx_usb.mpf
   gnuradio/branches/developers/thottelt/tx_usb/tx_usb.v
   gnuradio/branches/developers/thottelt/tx_usb/tx_usb_test.v
   gnuradio/branches/developers/thottelt/tx_usb/vsim.wlf
Log:
merge processes

Deleted: gnuradio/branches/developers/thottelt/tx_usb/tx_usb.cr.mti

Deleted: gnuradio/branches/developers/thottelt/tx_usb/tx_usb.mpf

Added: gnuradio/branches/developers/thottelt/tx_usb/tx_usb.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/tx_usb/tx_usb.mpf                     
        (rev 0)
+++ gnuradio/branches/developers/thottelt/tx_usb/tx_usb.mpf     2007-04-03 
00:40:46 UTC (rev 4849)
@@ -0,0 +1,286 @@
+[Library]
+
+; Altera specific primitive library mappings 
+
+vital2000 = $MODEL_TECH/../vital2000
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+std = $MODEL_TECH/../std
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+apex20k = $MODEL_TECH/../altera/vhdl/apex20k
+apex20ke = $MODEL_TECH/../altera/vhdl/apex20ke
+apexii = $MODEL_TECH/../altera/vhdl/apexii
+altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
+altera = $MODEL_TECH/../altera/vhdl/altera
+lpm = $MODEL_TECH/../altera/vhdl/220model
+220model = $MODEL_TECH/../altera/vhdl/220model
+alt_vtl = $MODEL_TECH/../altera/vhdl/alt_vtl
+flex6000 = $MODEL_TECH/../altera/vhdl/flex6000
+flex10ke = $MODEL_TECH/../altera/vhdl/flex10ke
+max = $MODEL_TECH/../altera/vhdl/max
+maxii = $MODEL_TECH/../altera/vhdl/maxii
+stratix = $MODEL_TECH/../altera/vhdl/stratix
+stratixii = $MODEL_TECH/../altera/vhdl/stratixii
+cyclone = $MODEL_TECH/../altera/vhdl/cyclone
+cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
+sgate = $MODEL_TECH/../altera/vhdl/sgate
+apex20k_ver = $MODEL_TECH/../altera/verilog/apex20k
+apex20ke_ver = $MODEL_TECH/../altera/verilog/apex20ke
+apexii_ver = $MODEL_TECH/../altera/verilog/apexii
+altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
+altera_ver = $MODEL_TECH/../altera/verilog/altera
+lpm_ver = $MODEL_TECH/../altera/verilog/220model
+220model_ver = $MODEL_TECH/../altera/verilog/220model
+alt_ver = $MODEL_TECH/../altera/verilog/alt_vtl
+flex6000_ver = $MODEL_TECH/../altera/verilog/flex6000
+flex10ke_ver = $MODEL_TECH/../altera/verilog/flex10ke
+max_ver = $MODEL_TECH/../altera/verilog/max
+maxii_ver = $MODEL_TECH/../altera/verilog/maxii
+stratix_ver = $MODEL_TECH/../altera/verilog/stratix
+stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
+cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
+cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
+sgate_ver = $MODEL_TECH/../altera/verilog/sgate
+stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
+stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
+
+work = work
+[vcom]
+; Turn on VHDL-1993 as the default. Normally is off.
+; VHDL93 = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; .ini file has Explict enable so that std_logic_signed/unsigned
+; will match synthesis tools behavior.
+ Explicit = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = false
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off inclusion of debugging info within design units. Default is to 
include.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;      -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+
+; RequireConfigForAllDefaultBinding = 1 
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units. Default is to 
include.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turns on incremental compilation of modules 
+; Incremental = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+resolution = 1ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100 ps
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license isn't available
+; License = plus
+
+; Stop the simulator after an assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history 
+;CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described 
+; in VHDL or Verilog format. For VHDL, PathSeparator = /
+; for Verilog, PathSeparator = .
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, or deposit 
+; or in other terms, fixed, wired or charged.
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated
+; else open files on first read or write
+; DelayFileOpen = 0
+
+; Control VHDL files opened for write
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control number of VHDL files open concurrently
+;   This number should always be less then the 
+;   current ulimit setting for max file descriptors
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; This controls the number of hierarchical regions displayed as
+; part of a signal name shown in the waveform window.  The default
+; value or a value of zero tells VSIM to display the full name.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit
+; packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of a generate statement label. Don't quote it.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is to be compressed.
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+[Project]
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 4
+Project_File_0 = ./usb_packet_fifo_test.v
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1175460531 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = ./usb_fifo_reader.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1175560289 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 1 
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_2 = ./usb_packet_fifo.v
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1175460531 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_3 = ./usb_fifo_reader_test.v
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1175538258 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ReOpenSourceFiles = 1
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick = 
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick = 
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick = 
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick = 
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick = 
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick = 
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick = 
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick = 
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick = 
+XML_DoubleClick = Edit
+XML_CustomDoubleClick = 
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick = 
+EditorState = {tabbed horizontal 1} {Z:/wc/tx_usb/usb_fifo_reader_test.v 0 1}
+Project_Major_Version = 6
+Project_Minor_Version = 1


Property changes on: gnuradio/branches/developers/thottelt/tx_usb/tx_usb.mpf
___________________________________________________________________
Name: svn:executable
   + *

Deleted: gnuradio/branches/developers/thottelt/tx_usb/tx_usb.v

Deleted: gnuradio/branches/developers/thottelt/tx_usb/tx_usb_test.v

Copied: gnuradio/branches/developers/thottelt/tx_usb/usb_fifo_reader.v (from 
rev 4838, gnuradio/branches/developers/thottelt/tx_usb/tx_usb.v)
===================================================================
--- gnuradio/branches/developers/thottelt/tx_usb/usb_fifo_reader.v              
                (rev 0)
+++ gnuradio/branches/developers/thottelt/tx_usb/usb_fifo_reader.v      
2007-04-03 00:40:46 UTC (rev 4849)
@@ -0,0 +1,140 @@
+module usb_fifo_reader (
+   input usb_clock,
+   input tx_clock,
+   input [15:0] usb_data,
+   input WR,
+   input reset,
+   output reg [15:0] tx_cmd_bus,
+   output reg [15:0] tx_chan_bus_0,
+   output reg [15:0] tx_chan_bus_1   ) ;
+   
+   // States
+   `define IDLE          3'd0
+   `define WAIT          3'd1
+   `define READ_TARGET   3'd2
+   `define READ_LENGTH   3'd3
+   `define FORWARD_DATA  3'd4
+   `define SKIP_REST     3'd5
+   
+   `define TXCHAN0       5'h0
+   `define TXCHAN1       5'h1
+   `define TXCMD         5'h1F
+   
+   reg [2:0] reader_state;
+   reg [2:0] reader_next_state;
+   reg [4:0] channel;
+   reg [8:0] pkt_length;
+   reg [8:0] read_length;
+   
+   // Fifo's flags
+   wire [15:0] fifodata ;
+   reg rdreq;
+   reg skip;
+   wire pkt_waiting;
+   
+   // FIFO
+   usb_packet_fifo tx_usb_fifo 
+     (  .reset(reset),
+        .clock_in(usb_clock), 
+        .clock_out(tx_clock),
+        .ram_data_in(usb_data),
+        .write_enable(WR),
+        .ram_data_out(fifodata),
+        .pkt_waiting(pkt_waiting),
+        .read_enable(rdreq), 
+        .skip_packet(skip)
+       );
+    
+    // FSM
+    always @(posedge tx_clock)
+    begin
+        if (reset) begin
+           reader_state <= `IDLE;
+           reader_next_state <= `IDLE;
+           rdreq <= 0;
+           skip <= 0;
+        end
+        else begin
+          reader_state = reader_next_state;
+          case(reader_state)
+            `IDLE: begin
+                  reader_next_state <= pkt_waiting ? `WAIT : `IDLE;
+                  rdreq <= pkt_waiting;
+               end
+            
+            // Wait for the fifo's data
+            `WAIT: begin
+                  reader_next_state <= `READ_TARGET;
+               end
+               
+            `READ_TARGET: begin
+                  reader_next_state <= `READ_LENGTH;
+                  channel = (fifodata & 16'h1F);
+                  
+                  // Forward data
+                  case (channel)
+                      `TXCHAN0: tx_chan_bus_0 = fifodata;
+                      `TXCHAN1: tx_chan_bus_1 = fifodata;
+                      `TXCMD: tx_cmd_bus = fifodata;
+                      //invalid channel -> channel 0;
+                      default:  tx_chan_bus_0 <= fifodata;
+                  endcase
+               end
+               
+            `READ_LENGTH: begin
+                  reader_next_state <= `FORWARD_DATA;
+                  
+                  // Plus two bytes for timestamp
+                  pkt_length <= (fifodata & 16'h1FF) + 2;
+                  read_length <= 9'd0;
+                  
+                  // Forward data
+                  case (channel)
+                      `TXCHAN0: tx_chan_bus_0 <= fifodata;
+                      `TXCHAN1: tx_chan_bus_1 <= fifodata;
+                      `TXCMD: tx_cmd_bus <= fifodata;
+                      //invalid channel -> channel 0;
+                      default:  tx_chan_bus_0 <= fifodata;
+                  endcase
+               end
+               
+            `FORWARD_DATA: begin
+                  read_length <= read_length + 2;
+                  
+                  // If end of payload...
+                  if (read_length == pkt_length) begin
+                     reader_next_state <= `SKIP_REST;
+                     // If the packet is 512 bytes, don't skip
+                     skip <= pkt_length < 506;
+                  end
+                  else if (read_length == pkt_length - 2) 
+                     rdreq <= 0;
+                    
+                  // Forward data
+                  case (channel)
+                      `TXCHAN0: tx_chan_bus_0 <= fifodata;
+                      `TXCHAN1: tx_chan_bus_1 <= fifodata;
+                      `TXCMD:   tx_cmd_bus <= fifodata;
+                      //invalid channel -> channel 0;
+                      default:  tx_chan_bus_0 <= fifodata;
+                  endcase
+               end
+               
+            `SKIP_REST: begin
+                  reader_next_state <= pkt_waiting ? `READ_TARGET : `IDLE;
+                  rdreq <= pkt_waiting;
+                  skip <= 0;
+               end
+            // reset
+            default: begin
+                reader_state <= `IDLE;
+                reader_next_state <= `IDLE;
+              end
+         endcase
+        end
+    end
+    
+endmodule
+       
+   
+   
\ No newline at end of file

Copied: gnuradio/branches/developers/thottelt/tx_usb/usb_fifo_reader_test.v 
(from rev 4838, gnuradio/branches/developers/thottelt/tx_usb/tx_usb_test.v)
===================================================================
--- gnuradio/branches/developers/thottelt/tx_usb/usb_fifo_reader_test.v         
                (rev 0)
+++ gnuradio/branches/developers/thottelt/tx_usb/usb_fifo_reader_test.v 
2007-04-03 00:40:46 UTC (rev 4849)
@@ -0,0 +1,104 @@
+module usb_fifo_reader_test () ;
+  
+//INPUTS 
+reg usb_clock;
+reg tx_clock;
+reg [15:0] usb_data;
+reg WR;
+reg reset;
+   
+//OUPUTS
+wire [15:0] tx_cmd;
+wire [15:0] tx_chan0;
+wire [15:0] tx_chan1;
+
+reg [15:0] i ;
+
+usb_fifo_reader reader (
+        .reset(reset), 
+        .usb_clock(usb_clock),  
+        .WR(WR), 
+        .tx_clock(tx_clock), 
+        .tx_cmd_bus(tx_cmd),
+        .tx_chan_bus_0(tx_chan0),
+        .tx_chan_bus_1(tx_chan1),
+        .usb_data(usb_data)
+    );
+
+
+// Initialize Inputs
+    initial begin
+        // Setup the initial conditions
+        reset = 1;
+        usb_clock = 0;
+        usb_data = 0;
+        WR = 0;
+        tx_clock = 0;
+        i = 0 ;
+
+        // Deassert the reset
+        #40 reset = 1'b0 ;
+
+        // Wait a few clocks
+        repeat (5) begin
+          @(posedge usb_clock)
+            reset = 1'b0 ;
+        end
+        
+        // Write one half full packet (channel 0)
+        repeat (256) begin
+          @(posedge usb_clock)
+            WR = 1'b1 ;
+            if (i == 1) 
+               // payload size
+               usb_data = 32;
+            else
+               usb_data = i ;
+          i = i + 1 ;
+        end
+        
+        i = 0;
+        
+        // Write one full packet (channel 1)
+        repeat (256) begin
+          @(posedge usb_clock)
+            WR = 1'b1 ;
+            if (i == 0) 
+               // channel
+               usb_data = 1;
+            else if (i == 1)
+               // payload size
+               usb_data = 504;
+            else
+               usb_data = i ;
+          i = i + 1 ;
+        end
+        
+        i = 0;
+        
+        // Write one half full packet (cmd)
+        repeat (256) begin
+          @(posedge usb_clock)
+            WR = 1'b1 ;
+            if (i == 0) 
+               // channel
+               usb_data = 16'h1F;
+            else if (i == 1)
+               // payload size
+               usb_data = 128;
+            else
+               usb_data = i ;
+          i = i + 1 ;
+        end
+        
+        @(posedge usb_clock) 
+          WR = 1'b0 ;
+    end
+
+always
+   #5 tx_clock = ~tx_clock ;
+    
+always
+   #13 usb_clock = ~usb_clock ;
+    
+endmodule

Deleted: gnuradio/branches/developers/thottelt/tx_usb/vsim.wlf