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[Commit-gnuradio] r4941 - in gnuradio/branches/developers/jcorgan/sar-fe
|
From: |
jcorgan |
|
Subject: |
[Commit-gnuradio] r4941 - in gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src: fpga/rbf/rev2 fpga/rbf/rev4 fpga/toplevel python |
|
Date: |
Tue, 10 Apr 2007 01:18:59 -0600 (MDT) |
Author: jcorgan
Date: 2007-04-10 01:18:59 -0600 (Tue, 10 Apr 2007)
New Revision: 4941
Added:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/dacpll.v
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev2/usrp_sar.rbf
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev4/usrp_sar.rbf
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/Makefile.am
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/sar_tx.py
Log:
Work in progress. Attempting to use FPGA PLL to mimic AD9862 CLKOUT2 signal,
not yet working, but progress.
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev2/usrp_sar.rbf
===================================================================
(Binary files differ)
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev4/usrp_sar.rbf
===================================================================
(Binary files differ)
Added:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/dacpll.v
===================================================================
---
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/dacpll.v
(rev 0)
+++
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/dacpll.v
2007-04-10 07:18:59 UTC (rev 4941)
@@ -0,0 +1,291 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: dacpll.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 7.0 Build 33 02/05/2007 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2007 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module dacpll (
+ areset,
+ inclk0,
+ c0);
+
+ input areset;
+ input inclk0;
+ output c0;
+
+ wire [5:0] sub_wire0;
+ wire [0:0] sub_wire4 = 1'h0;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire sub_wire2 = inclk0;
+ wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
+
+ altpll altpll_component (
+ .inclk (sub_wire3),
+ .areset (areset),
+ .clk (sub_wire0),
+ .activeclock (),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b1),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbout (),
+ .locked (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.clk0_divide_by = 1,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 2,
+ altpll_component.clk0_phase_shift = "4000",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 15625,
+ altpll_component.intended_device_family = "Cyclone",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "AUTO",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_USED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_UNUSED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "5.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "5000"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC
"@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_inst.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_bb.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_waveforms.html TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_wave*.jpg FALSE FALSE
+// Retrieval info: LIB_FILE: altera_mf
Property changes on:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/dacpll.v
___________________________________________________________________
Name: svn:executable
+ *
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
===================================================================
---
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
2007-04-10 06:22:39 UTC (rev 4940)
+++
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
2007-04-10 07:18:59 UTC (rev 4941)
@@ -327,7 +327,6 @@
# ==================
set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS
OFF -section_id SCLK
# end CLOCK(SCLK)
# ---------------
@@ -339,7 +338,6 @@
# ==================
set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS
OFF -section_id master_clk
# end CLOCK(master_clk)
# ---------------------
@@ -351,7 +349,6 @@
# ==================
set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS
OFF -section_id usbclk
# end CLOCK(usbclk)
# -----------------
@@ -370,6 +367,7 @@
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition
-to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name VERILOG_FILE dacpll.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/cordic_stage.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v
@@ -387,4 +385,4 @@
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE usrp_sar.v
\ No newline at end of file
+set_global_assignment -name VERILOG_FILE usrp_sar.v
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
===================================================================
---
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
2007-04-10 06:22:39 UTC (rev 4940)
+++
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
2007-04-10 07:18:59 UTC (rev 4941)
@@ -107,19 +107,25 @@
// Transmit Side
wire [15:0] tx_i, tx_q;
+ reg [15:0] tx_a_reg;
wire [15:0] tx_debug;
-
- // Transmitter creates a new output sample per tx_sample_strobe
- // This limits the range from -16MHz to +16MHz. It's not possible with the
- // USRP1 to use the full capacity of the DACs as the CLKOUT2 pin is not
wired
- // to the FPGA.
- sar_tx
transmitter(.clk_i(clk64),.rst_i(sar_reset),.ena_i(enable_tx),.strobe_i(tx_sample_strobe),
+
+ // Transmitter creates a new output sample per clk64
+ sar_tx
transmitter(.clk_i(clk64),.rst_i(sar_reset),.ena_i(enable_tx),.strobe_i(1'b1),
.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
.tx_i_o(tx_i),.tx_q_o(tx_q),.debug_o(tx_debug));
- assign TXSYNC_A = tx_sample_strobe;
- assign tx_a = tx_sample_strobe ? tx_i[15:2] : tx_q[15:2];
+ // This "re-creates" the AD9862 CLKOUT2 signal as CLKOUT2 is not wired to
the FPGA
+ // The PLL phase must be experimentally determined
+ wire clk128;
+ dacpll pll128(.areset(rst_i),.inclk0(clk64),.c0(clk128));
+ always @(posedge clk128)
+ tx_a_reg <= clk64 ? tx_i : tx_q;
+
+ assign TXSYNC_A = clk64;
+ assign tx_a = tx_a_reg[15:2];
+
assign tx_b = 14'b0;
assign TXSYNC_B = 0;
@@ -138,8 +144,6 @@
.ddc2_in_i(),.ddc2_in_q(),
.ddc3_in_i(),.ddc3_in_q(),.rx_numchan(rx_numchan));
-
-
wire [15:0] rx_i, rx_q;
wire rx_strobe;
wire [15:0] rx_debug;
Property changes on:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python
___________________________________________________________________
Name: svn:ignore
- Makefile
Makefile.in
run_tests
+ Makefile
Makefile.in
run_tests
*.pyc
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/Makefile.am
===================================================================
---
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/Makefile.am
2007-04-10 06:22:39 UTC (rev 4940)
+++
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/Makefile.am
2007-04-10 07:18:59 UTC (rev 4941)
@@ -23,3 +23,5 @@
EXTRA_DIST = \
sar_tx.py
+
+MOSTLYCLEANFILES = *~ *.pyc *.pyo
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/sar_tx.py
===================================================================
--- gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/sar_tx.py
2007-04-10 06:22:39 UTC (rev 4940)
+++ gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/sar_tx.py
2007-04-10 07:18:59 UTC (rev 4941)
@@ -9,12 +9,16 @@
class sar_tx:
def __init__(self):
self.trans = usrp.sink_s(fpga_filename='usrp_sar.rbf')
+ self.set_tx_intfc(0x09)
+ self.set_tx_dig(0x11)
+ self.set_tx_dll(0x49)
+ self.set_tx_clkout(0x00)
def set_amplitude(self, amplitude):
self.trans._write_fpga_reg(usrp.FR_USER_0, int(amplitude))
def tune(self, freq):
- ftw = int(freq*(2**32)/32e6)
+ ftw = int(freq*(2**32)/64e6)
self.trans._write_fpga_reg(usrp.FR_USER_1, ftw)
def set_phase(self, phase):
@@ -27,6 +31,30 @@
def stop(self):
self.trans.stop()
+ def set_tx_intfc(self, value):
+ self.trans._write_9862(0, 18, value)
+
+ def tx_intfc(self):
+ return self.trans._read_9862(0, 18)
+
+ def set_tx_dig(self, value):
+ self.trans._write_9862(0, 19, value)
+
+ def tx_dig(self):
+ return self.trans._read_9862(0, 19)
+
+ def set_tx_dll(self, value):
+ self.trans._write_9862(0, 24, value)
+
+ def tx_dll(self):
+ return self.trans._read_9862(0, 24)
+
+ def set_tx_clkout(self, value):
+ self.trans._write_9862(0, 25, value)
+
+ def tx_clkout(self):
+ return self.trans._read_9862(0, 25)
+
def test_transmit(options):
t = sar_tx()
t.set_amplitude(options.amplitude)
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- [Commit-gnuradio] r4941 - in gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src: fpga/rbf/rev2 fpga/rbf/rev4 fpga/toplevel python,
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