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[Commit-gnuradio] r5011 - gnuradio/branches/developers/matt/u2f/opencore
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From: |
matt |
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Subject: |
[Commit-gnuradio] r5011 - gnuradio/branches/developers/matt/u2f/opencores/wb_conbus/rtl/verilog |
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Date: |
Sun, 15 Apr 2007 21:17:04 -0600 (MDT) |
Author: matt
Date: 2007-04-15 21:17:04 -0600 (Sun, 15 Apr 2007)
New Revision: 5011
Modified:
gnuradio/branches/developers/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v
Log:
LOCAL CHANGE -- allow for parameterization of bus widths
Modified:
gnuradio/branches/developers/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v
2007-04-16 03:16:21 UTC (rev 5010)
+++
gnuradio/branches/developers/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v
2007-04-16 03:17:04 UTC (rev 5011)
@@ -46,14 +46,6 @@
// or 150 SLICE if using tri-state bus.
//
`include "wb_conbus_defines.v"
-`define dw 32 // Data bus Width
-`define aw 32 // Address bus Width
-`define sw `dw / 8 // Number of Select Lines
-`define mbusw `aw + `sw + `dw +4 //address width
+ byte select width + dat width + cyc + we + stb +cab , input from master
interface
-`define sbusw 3 // ack + err + rty, input from
slave interface
-`define mselectw 8 // number of masters
-`define sselectw 8 // number of slavers
-
//`define WB_USE_TRISTATE
@@ -144,7 +136,15 @@
parameter s6_addr = 8'h96; // slave 6 address
parameter s7_addr = 8'h97; // slave 7 address
+ parameter dw = 32; // Data bus Width
+ parameter aw = 32; // Address bus Width
+ parameter sw = dw / 8; // Number of Select Lines
+ parameter mbusw = aw + sw + dw + 4; //address width + byte
select width + dat width + cyc + we + stb +cab , input from master interface
+ parameter sbusw = 3; // ack + err + rty, input from slave
interface
+ parameter mselectw = 8; // number of masters
+ parameter sselectw = 8; // number of slavers
+
////////////////////////////////////////////////////////////////////
//
// Module IOs
@@ -153,10 +153,10 @@
input clk_i, rst_i;
// Master 0 Interface
-input [`dw-1:0] m0_dat_i;
-output [`dw-1:0] m0_dat_o;
-input [`aw-1:0] m0_adr_i;
-input [`sw-1:0] m0_sel_i;
+input [dw-1:0] m0_dat_i;
+output [dw-1:0] m0_dat_o;
+input [aw-1:0] m0_adr_i;
+input [sw-1:0] m0_sel_i;
input m0_we_i;
input m0_cyc_i;
input m0_stb_i;
@@ -166,10 +166,10 @@
output m0_rty_o;
// Master 1 Interface
-input [`dw-1:0] m1_dat_i;
-output [`dw-1:0] m1_dat_o;
-input [`aw-1:0] m1_adr_i;
-input [`sw-1:0] m1_sel_i;
+input [dw-1:0] m1_dat_i;
+output [dw-1:0] m1_dat_o;
+input [aw-1:0] m1_adr_i;
+input [sw-1:0] m1_sel_i;
input m1_we_i;
input m1_cyc_i;
input m1_stb_i;
@@ -179,10 +179,10 @@
output m1_rty_o;
// Master 2 Interface
-input [`dw-1:0] m2_dat_i;
-output [`dw-1:0] m2_dat_o;
-input [`aw-1:0] m2_adr_i;
-input [`sw-1:0] m2_sel_i;
+input [dw-1:0] m2_dat_i;
+output [dw-1:0] m2_dat_o;
+input [aw-1:0] m2_adr_i;
+input [sw-1:0] m2_sel_i;
input m2_we_i;
input m2_cyc_i;
input m2_stb_i;
@@ -192,10 +192,10 @@
output m2_rty_o;
// Master 3 Interface
-input [`dw-1:0] m3_dat_i;
-output [`dw-1:0] m3_dat_o;
-input [`aw-1:0] m3_adr_i;
-input [`sw-1:0] m3_sel_i;
+input [dw-1:0] m3_dat_i;
+output [dw-1:0] m3_dat_o;
+input [aw-1:0] m3_adr_i;
+input [sw-1:0] m3_sel_i;
input m3_we_i;
input m3_cyc_i;
input m3_stb_i;
@@ -205,10 +205,10 @@
output m3_rty_o;
// Master 4 Interface
-input [`dw-1:0] m4_dat_i;
-output [`dw-1:0] m4_dat_o;
-input [`aw-1:0] m4_adr_i;
-input [`sw-1:0] m4_sel_i;
+input [dw-1:0] m4_dat_i;
+output [dw-1:0] m4_dat_o;
+input [aw-1:0] m4_adr_i;
+input [sw-1:0] m4_sel_i;
input m4_we_i;
input m4_cyc_i;
input m4_stb_i;
@@ -218,10 +218,10 @@
output m4_rty_o;
// Master 5 Interface
-input [`dw-1:0] m5_dat_i;
-output [`dw-1:0] m5_dat_o;
-input [`aw-1:0] m5_adr_i;
-input [`sw-1:0] m5_sel_i;
+input [dw-1:0] m5_dat_i;
+output [dw-1:0] m5_dat_o;
+input [aw-1:0] m5_adr_i;
+input [sw-1:0] m5_sel_i;
input m5_we_i;
input m5_cyc_i;
input m5_stb_i;
@@ -231,10 +231,10 @@
output m5_rty_o;
// Master 6 Interface
-input [`dw-1:0] m6_dat_i;
-output [`dw-1:0] m6_dat_o;
-input [`aw-1:0] m6_adr_i;
-input [`sw-1:0] m6_sel_i;
+input [dw-1:0] m6_dat_i;
+output [dw-1:0] m6_dat_o;
+input [aw-1:0] m6_adr_i;
+input [sw-1:0] m6_sel_i;
input m6_we_i;
input m6_cyc_i;
input m6_stb_i;
@@ -244,10 +244,10 @@
output m6_rty_o;
// Master 7 Interface
-input [`dw-1:0] m7_dat_i;
-output [`dw-1:0] m7_dat_o;
-input [`aw-1:0] m7_adr_i;
-input [`sw-1:0] m7_sel_i;
+input [dw-1:0] m7_dat_i;
+output [dw-1:0] m7_dat_o;
+input [aw-1:0] m7_adr_i;
+input [sw-1:0] m7_sel_i;
input m7_we_i;
input m7_cyc_i;
input m7_stb_i;
@@ -257,10 +257,10 @@
output m7_rty_o;
// Slave 0 Interface
-input [`dw-1:0] s0_dat_i;
-output [`dw-1:0] s0_dat_o;
-output [`aw-1:0] s0_adr_o;
-output [`sw-1:0] s0_sel_o;
+input [dw-1:0] s0_dat_i;
+output [dw-1:0] s0_dat_o;
+output [aw-1:0] s0_adr_o;
+output [sw-1:0] s0_sel_o;
output s0_we_o;
output s0_cyc_o;
output s0_stb_o;
@@ -270,10 +270,10 @@
input s0_rty_i;
// Slave 1 Interface
-input [`dw-1:0] s1_dat_i;
-output [`dw-1:0] s1_dat_o;
-output [`aw-1:0] s1_adr_o;
-output [`sw-1:0] s1_sel_o;
+input [dw-1:0] s1_dat_i;
+output [dw-1:0] s1_dat_o;
+output [aw-1:0] s1_adr_o;
+output [sw-1:0] s1_sel_o;
output s1_we_o;
output s1_cyc_o;
output s1_stb_o;
@@ -283,10 +283,10 @@
input s1_rty_i;
// Slave 2 Interface
-input [`dw-1:0] s2_dat_i;
-output [`dw-1:0] s2_dat_o;
-output [`aw-1:0] s2_adr_o;
-output [`sw-1:0] s2_sel_o;
+input [dw-1:0] s2_dat_i;
+output [dw-1:0] s2_dat_o;
+output [aw-1:0] s2_adr_o;
+output [sw-1:0] s2_sel_o;
output s2_we_o;
output s2_cyc_o;
output s2_stb_o;
@@ -296,10 +296,10 @@
input s2_rty_i;
// Slave 3 Interface
-input [`dw-1:0] s3_dat_i;
-output [`dw-1:0] s3_dat_o;
-output [`aw-1:0] s3_adr_o;
-output [`sw-1:0] s3_sel_o;
+input [dw-1:0] s3_dat_i;
+output [dw-1:0] s3_dat_o;
+output [aw-1:0] s3_adr_o;
+output [sw-1:0] s3_sel_o;
output s3_we_o;
output s3_cyc_o;
output s3_stb_o;
@@ -309,10 +309,10 @@
input s3_rty_i;
// Slave 4 Interface
-input [`dw-1:0] s4_dat_i;
-output [`dw-1:0] s4_dat_o;
-output [`aw-1:0] s4_adr_o;
-output [`sw-1:0] s4_sel_o;
+input [dw-1:0] s4_dat_i;
+output [dw-1:0] s4_dat_o;
+output [aw-1:0] s4_adr_o;
+output [sw-1:0] s4_sel_o;
output s4_we_o;
output s4_cyc_o;
output s4_stb_o;
@@ -322,10 +322,10 @@
input s4_rty_i;
// Slave 5 Interface
-input [`dw-1:0] s5_dat_i;
-output [`dw-1:0] s5_dat_o;
-output [`aw-1:0] s5_adr_o;
-output [`sw-1:0] s5_sel_o;
+input [dw-1:0] s5_dat_i;
+output [dw-1:0] s5_dat_o;
+output [aw-1:0] s5_adr_o;
+output [sw-1:0] s5_sel_o;
output s5_we_o;
output s5_cyc_o;
output s5_stb_o;
@@ -335,10 +335,10 @@
input s5_rty_i;
// Slave 6 Interface
-input [`dw-1:0] s6_dat_i;
-output [`dw-1:0] s6_dat_o;
-output [`aw-1:0] s6_adr_o;
-output [`sw-1:0] s6_sel_o;
+input [dw-1:0] s6_dat_i;
+output [dw-1:0] s6_dat_o;
+output [aw-1:0] s6_adr_o;
+output [sw-1:0] s6_sel_o;
output s6_we_o;
output s6_cyc_o;
output s6_stb_o;
@@ -348,10 +348,10 @@
input s6_rty_i;
// Slave 7 Interface
-input [`dw-1:0] s7_dat_i;
-output [`dw-1:0] s7_dat_o;
-output [`aw-1:0] s7_adr_o;
-output [`sw-1:0] s7_sel_o;
+input [dw-1:0] s7_dat_i;
+output [dw-1:0] s7_dat_o;
+output [aw-1:0] s7_adr_o;
+output [sw-1:0] s7_sel_o;
output s7_we_o;
output s7_cyc_o;
output s7_stb_o;
@@ -366,16 +366,16 @@
// Local wires
//
-wire [`mselectw -1:0] i_gnt_arb;
+wire [mselectw -1:0] i_gnt_arb;
wire [2:0] gnt;
-reg [`sselectw -1:0] i_ssel_dec;
+reg [sselectw -1:0] i_ssel_dec;
`ifdef WB_USE_TRISTATE
-wire [`mbusw -1:0] i_bus_m;
+wire [mbusw -1:0] i_bus_m;
`else
-reg [`mbusw -1:0] i_bus_m; // internal share bus,
master data and control to slave
+reg [mbusw -1:0] i_bus_m; // internal share bus,
master data and control to slave
`endif
-wire [`dw -1:0] i_dat_s; // internal share bus ,
slave data to master
-wire [`sbusw -1:0] i_bus_s; // internal share bus ,
slave control to master
+wire [dw -1:0] i_dat_s; // internal share bus ,
slave data to master
+wire [sbusw -1:0] i_bus_s; // internal share bus ,
slave control to master
@@ -431,42 +431,42 @@
// Slave output interface
//
// slave0
-assign {s0_adr_o, s0_sel_o, s0_dat_o, s0_we_o, s0_cab_o,s0_cyc_o} =
i_bus_m[`mbusw -1:1];
+assign {s0_adr_o, s0_sel_o, s0_dat_o, s0_we_o, s0_cab_o,s0_cyc_o} =
i_bus_m[mbusw -1:1];
assign s0_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[0]; // stb_o = cyc_i &
stb_i & i_ssel_dec
// slave1
-assign {s1_adr_o, s1_sel_o, s1_dat_o, s1_we_o, s1_cab_o, s1_cyc_o} =
i_bus_m[`mbusw -1:1];
+assign {s1_adr_o, s1_sel_o, s1_dat_o, s1_we_o, s1_cab_o, s1_cyc_o} =
i_bus_m[mbusw -1:1];
assign s1_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[1];
// slave2
-assign {s2_adr_o, s2_sel_o, s2_dat_o, s2_we_o, s2_cab_o, s2_cyc_o} =
i_bus_m[`mbusw -1:1];
+assign {s2_adr_o, s2_sel_o, s2_dat_o, s2_we_o, s2_cab_o, s2_cyc_o} =
i_bus_m[mbusw -1:1];
assign s2_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[2];
// slave3
-assign {s3_adr_o, s3_sel_o, s3_dat_o, s3_we_o, s3_cab_o, s3_cyc_o} =
i_bus_m[`mbusw -1:1];
+assign {s3_adr_o, s3_sel_o, s3_dat_o, s3_we_o, s3_cab_o, s3_cyc_o} =
i_bus_m[mbusw -1:1];
assign s3_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[3];
// slave4
-assign {s4_adr_o, s4_sel_o, s4_dat_o, s4_we_o, s4_cab_o, s4_cyc_o} =
i_bus_m[`mbusw -1:1];
+assign {s4_adr_o, s4_sel_o, s4_dat_o, s4_we_o, s4_cab_o, s4_cyc_o} =
i_bus_m[mbusw -1:1];
assign s4_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[4];
// slave5
-assign {s5_adr_o, s5_sel_o, s5_dat_o, s5_we_o, s5_cab_o, s5_cyc_o} =
i_bus_m[`mbusw -1:1];
+assign {s5_adr_o, s5_sel_o, s5_dat_o, s5_we_o, s5_cab_o, s5_cyc_o} =
i_bus_m[mbusw -1:1];
assign s5_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[5];
// slave6
-assign {s6_adr_o, s6_sel_o, s6_dat_o, s6_we_o, s6_cab_o, s6_cyc_o} =
i_bus_m[`mbusw -1:1];
+assign {s6_adr_o, s6_sel_o, s6_dat_o, s6_we_o, s6_cab_o, s6_cyc_o} =
i_bus_m[mbusw -1:1];
assign s6_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[6];
// slave7
-assign {s7_adr_o, s7_sel_o, s7_dat_o, s7_we_o, s7_cab_o, s7_cyc_o} =
i_bus_m[`mbusw -1:1];
+assign {s7_adr_o, s7_sel_o, s7_dat_o, s7_we_o, s7_cab_o, s7_cyc_o} =
i_bus_m[mbusw -1:1];
assign s7_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[7];
///////////////////////////////////////
@@ -522,7 +522,7 @@
i_ssel_dec[4] ? s4_dat_i :
i_ssel_dec[5] ? s5_dat_i :
i_ssel_dec[6] ? s6_dat_i :
- i_ssel_dec[7] ? s7_dat_i : {`dw{1'b0}};
+ i_ssel_dec[7] ? s7_dat_i : {dw{1'b0}};
`endif
//
// arbitor
@@ -569,86 +569,86 @@
//
// decode all master address before arbitor for running faster
//
-assign m0_ssel_dec[0] = (m0_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);
-assign m0_ssel_dec[1] = (m0_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);
-assign m0_ssel_dec[2] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);
-assign m0_ssel_dec[3] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);
-assign m0_ssel_dec[4] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);
-assign m0_ssel_dec[5] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);
-assign m0_ssel_dec[6] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);
-assign m0_ssel_dec[7] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);
+assign m0_ssel_dec[0] = (m0_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr);
+assign m0_ssel_dec[1] = (m0_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr);
+assign m0_ssel_dec[2] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == s2_addr);
+assign m0_ssel_dec[3] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == s3_addr);
+assign m0_ssel_dec[4] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == s4_addr);
+assign m0_ssel_dec[5] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == s5_addr);
+assign m0_ssel_dec[6] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == s6_addr);
+assign m0_ssel_dec[7] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == s7_addr);
-assign m1_ssel_dec[0] = (m1_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);
-assign m1_ssel_dec[1] = (m1_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);
-assign m1_ssel_dec[2] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);
-assign m1_ssel_dec[3] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);
-assign m1_ssel_dec[4] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);
-assign m1_ssel_dec[5] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);
-assign m1_ssel_dec[6] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);
-assign m1_ssel_dec[7] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);
+assign m1_ssel_dec[0] = (m1_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr);
+assign m1_ssel_dec[1] = (m1_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr);
+assign m1_ssel_dec[2] = (m1_adr_i[aw -1 : aw - s27_addr_w ] == s2_addr);
+assign m1_ssel_dec[3] = (m1_adr_i[aw -1 : aw - s27_addr_w ] == s3_addr);
+assign m1_ssel_dec[4] = (m1_adr_i[aw -1 : aw - s27_addr_w ] == s4_addr);
+assign m1_ssel_dec[5] = (m1_adr_i[aw -1 : aw - s27_addr_w ] == s5_addr);
+assign m1_ssel_dec[6] = (m1_adr_i[aw -1 : aw - s27_addr_w ] == s6_addr);
+assign m1_ssel_dec[7] = (m1_adr_i[aw -1 : aw - s27_addr_w ] == s7_addr);
-assign m2_ssel_dec[0] = (m2_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);
-assign m2_ssel_dec[1] = (m2_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);
-assign m2_ssel_dec[2] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);
-assign m2_ssel_dec[3] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);
-assign m2_ssel_dec[4] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);
-assign m2_ssel_dec[5] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);
-assign m2_ssel_dec[6] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);
-assign m2_ssel_dec[7] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);
+assign m2_ssel_dec[0] = (m2_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr);
+assign m2_ssel_dec[1] = (m2_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr);
+assign m2_ssel_dec[2] = (m2_adr_i[aw -1 : aw - s27_addr_w ] == s2_addr);
+assign m2_ssel_dec[3] = (m2_adr_i[aw -1 : aw - s27_addr_w ] == s3_addr);
+assign m2_ssel_dec[4] = (m2_adr_i[aw -1 : aw - s27_addr_w ] == s4_addr);
+assign m2_ssel_dec[5] = (m2_adr_i[aw -1 : aw - s27_addr_w ] == s5_addr);
+assign m2_ssel_dec[6] = (m2_adr_i[aw -1 : aw - s27_addr_w ] == s6_addr);
+assign m2_ssel_dec[7] = (m2_adr_i[aw -1 : aw - s27_addr_w ] == s7_addr);
-assign m3_ssel_dec[0] = (m3_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);
-assign m3_ssel_dec[1] = (m3_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);
-assign m3_ssel_dec[2] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);
-assign m3_ssel_dec[3] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);
-assign m3_ssel_dec[4] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);
-assign m3_ssel_dec[5] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);
-assign m3_ssel_dec[6] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);
-assign m3_ssel_dec[7] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);
+assign m3_ssel_dec[0] = (m3_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr);
+assign m3_ssel_dec[1] = (m3_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr);
+assign m3_ssel_dec[2] = (m3_adr_i[aw -1 : aw - s27_addr_w ] == s2_addr);
+assign m3_ssel_dec[3] = (m3_adr_i[aw -1 : aw - s27_addr_w ] == s3_addr);
+assign m3_ssel_dec[4] = (m3_adr_i[aw -1 : aw - s27_addr_w ] == s4_addr);
+assign m3_ssel_dec[5] = (m3_adr_i[aw -1 : aw - s27_addr_w ] == s5_addr);
+assign m3_ssel_dec[6] = (m3_adr_i[aw -1 : aw - s27_addr_w ] == s6_addr);
+assign m3_ssel_dec[7] = (m3_adr_i[aw -1 : aw - s27_addr_w ] == s7_addr);
-assign m4_ssel_dec[0] = (m4_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);
-assign m4_ssel_dec[1] = (m4_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);
-assign m4_ssel_dec[2] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);
-assign m4_ssel_dec[3] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);
-assign m4_ssel_dec[4] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);
-assign m4_ssel_dec[5] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);
-assign m4_ssel_dec[6] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);
-assign m4_ssel_dec[7] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);
+assign m4_ssel_dec[0] = (m4_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr);
+assign m4_ssel_dec[1] = (m4_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr);
+assign m4_ssel_dec[2] = (m4_adr_i[aw -1 : aw - s27_addr_w ] == s2_addr);
+assign m4_ssel_dec[3] = (m4_adr_i[aw -1 : aw - s27_addr_w ] == s3_addr);
+assign m4_ssel_dec[4] = (m4_adr_i[aw -1 : aw - s27_addr_w ] == s4_addr);
+assign m4_ssel_dec[5] = (m4_adr_i[aw -1 : aw - s27_addr_w ] == s5_addr);
+assign m4_ssel_dec[6] = (m4_adr_i[aw -1 : aw - s27_addr_w ] == s6_addr);
+assign m4_ssel_dec[7] = (m4_adr_i[aw -1 : aw - s27_addr_w ] == s7_addr);
-assign m5_ssel_dec[0] = (m5_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);
-assign m5_ssel_dec[1] = (m5_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);
-assign m5_ssel_dec[2] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);
-assign m5_ssel_dec[3] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);
-assign m5_ssel_dec[4] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);
-assign m5_ssel_dec[5] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);
-assign m5_ssel_dec[6] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);
-assign m5_ssel_dec[7] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);
+assign m5_ssel_dec[0] = (m5_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr);
+assign m5_ssel_dec[1] = (m5_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr);
+assign m5_ssel_dec[2] = (m5_adr_i[aw -1 : aw - s27_addr_w ] == s2_addr);
+assign m5_ssel_dec[3] = (m5_adr_i[aw -1 : aw - s27_addr_w ] == s3_addr);
+assign m5_ssel_dec[4] = (m5_adr_i[aw -1 : aw - s27_addr_w ] == s4_addr);
+assign m5_ssel_dec[5] = (m5_adr_i[aw -1 : aw - s27_addr_w ] == s5_addr);
+assign m5_ssel_dec[6] = (m5_adr_i[aw -1 : aw - s27_addr_w ] == s6_addr);
+assign m5_ssel_dec[7] = (m5_adr_i[aw -1 : aw - s27_addr_w ] == s7_addr);
-assign m6_ssel_dec[0] = (m6_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);
-assign m6_ssel_dec[1] = (m6_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);
-assign m6_ssel_dec[2] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);
-assign m6_ssel_dec[3] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);
-assign m6_ssel_dec[4] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);
-assign m6_ssel_dec[5] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);
-assign m6_ssel_dec[6] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);
-assign m6_ssel_dec[7] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);
+assign m6_ssel_dec[0] = (m6_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr);
+assign m6_ssel_dec[1] = (m6_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr);
+assign m6_ssel_dec[2] = (m6_adr_i[aw -1 : aw - s27_addr_w ] == s2_addr);
+assign m6_ssel_dec[3] = (m6_adr_i[aw -1 : aw - s27_addr_w ] == s3_addr);
+assign m6_ssel_dec[4] = (m6_adr_i[aw -1 : aw - s27_addr_w ] == s4_addr);
+assign m6_ssel_dec[5] = (m6_adr_i[aw -1 : aw - s27_addr_w ] == s5_addr);
+assign m6_ssel_dec[6] = (m6_adr_i[aw -1 : aw - s27_addr_w ] == s6_addr);
+assign m6_ssel_dec[7] = (m6_adr_i[aw -1 : aw - s27_addr_w ] == s7_addr);
-assign m7_ssel_dec[0] = (m7_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);
-assign m7_ssel_dec[1] = (m7_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);
-assign m7_ssel_dec[2] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);
-assign m7_ssel_dec[3] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);
-assign m7_ssel_dec[4] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);
-assign m7_ssel_dec[5] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);
-assign m7_ssel_dec[6] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);
-assign m7_ssel_dec[7] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);
+assign m7_ssel_dec[0] = (m7_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr);
+assign m7_ssel_dec[1] = (m7_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr);
+assign m7_ssel_dec[2] = (m7_adr_i[aw -1 : aw - s27_addr_w ] == s2_addr);
+assign m7_ssel_dec[3] = (m7_adr_i[aw -1 : aw - s27_addr_w ] == s3_addr);
+assign m7_ssel_dec[4] = (m7_adr_i[aw -1 : aw - s27_addr_w ] == s4_addr);
+assign m7_ssel_dec[5] = (m7_adr_i[aw -1 : aw - s27_addr_w ] == s5_addr);
+assign m7_ssel_dec[6] = (m7_adr_i[aw -1 : aw - s27_addr_w ] == s6_addr);
+assign m7_ssel_dec[7] = (m7_adr_i[aw -1 : aw - s27_addr_w ] == s7_addr);
-//assign i_ssel_dec[0] = (i_bus_m[`mbusw -1 : `mbusw - s0_addr_w ] == s0_addr);
-//assign i_ssel_dec[1] = (i_bus_m[`mbusw -1 : `mbusw - s1_addr_w ] == s1_addr);
-//assign i_ssel_dec[2] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] ==
s2_addr);
-//assign i_ssel_dec[3] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] ==
s3_addr);
-//assign i_ssel_dec[4] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] ==
s4_addr);
-//assign i_ssel_dec[5] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] ==
s5_addr);
-//assign i_ssel_dec[6] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] ==
s6_addr);
-//assign i_ssel_dec[7] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] ==
s7_addr);
+//assign i_ssel_dec[0] = (i_bus_m[mbusw -1 : mbusw - s0_addr_w ] == s0_addr);
+//assign i_ssel_dec[1] = (i_bus_m[mbusw -1 : mbusw - s1_addr_w ] == s1_addr);
+//assign i_ssel_dec[2] = (i_bus_m[mbusw -1 : mbusw - s27_addr_w ] == s2_addr);
+//assign i_ssel_dec[3] = (i_bus_m[mbusw -1 : mbusw - s27_addr_w ] == s3_addr);
+//assign i_ssel_dec[4] = (i_bus_m[mbusw -1 : mbusw - s27_addr_w ] == s4_addr);
+//assign i_ssel_dec[5] = (i_bus_m[mbusw -1 : mbusw - s27_addr_w ] == s5_addr);
+//assign i_ssel_dec[6] = (i_bus_m[mbusw -1 : mbusw - s27_addr_w ] == s6_addr);
+//assign i_ssel_dec[7] = (i_bus_m[mbusw -1 : mbusw - s27_addr_w ] == s7_addr);
endmodule
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