[Commit-gnuradio] r5014 - in gnuradio/branches/developers/matt/u2f/opencores/aemb: CVS rtl/verilog rtl/verilog/CVS sim sim/CVS

[matt]

Author: matt
Date: 2007-04-15 21:18:49 -0600 (Sun, 15 Apr 2007)
New Revision: 5014

Removed:
   gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Entries.Log
Modified:
   gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Entries
   gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
   
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
   gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Entries
   gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/cversim
Log:
keep up with upstream, remove Entries.Log


Modified: gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Entries    
2007-04-16 03:17:59 UTC (rev 5013)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Entries    
2007-04-16 03:18:49 UTC (rev 5014)
@@ -1,5 +1,4 @@
-D/doc////
 D/rtl////
 D/sim////
 D/sw////
-D/syn////
+D/doc////

Deleted: gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Entries.Log

Modified: 
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
===================================================================
--- 
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries    
    2007-04-16 03:17:59 UTC (rev 5013)
+++ 
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries    
    2007-04-16 03:18:49 UTC (rev 5014)
@@ -3,6 +3,7 @@
 /aeMB_core.v/1.3/Wed Apr 11 06:30:44 2007//
 /aeMB_decode.v/1.4/Wed Apr 11 06:30:44 2007//
 /aeMB_fetch.v/1.3/Wed Apr 11 06:30:44 2007//
-/aeMB_testbench.v/1.4/Wed Apr 11 06:30:44 2007//
-/aeMB_regfile.v/1.7/Wed Apr 11 20:57:31 2007//
+/aeMB_regfile.v/1.8/Sat Apr 14 06:52:57 2007//
+/aeMB_ucore.v/1.1/Fri Apr 13 13:02:34 2007//
+/aeMB_wbbus.v/1.1/Fri Apr 13 13:02:34 2007//
 D

Modified: 
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
===================================================================
--- 
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v 
    2007-04-16 03:17:59 UTC (rev 5013)
+++ 
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v 
    2007-04-16 03:18:49 UTC (rev 5014)
@@ -1,5 +1,5 @@
 /*
- * $Id: aeMB_regfile.v,v 1.7 2007/04/11 16:30:06 sybreon Exp $
+ * $Id: aeMB_regfile.v,v 1.8 2007/04/12 20:21:33 sybreon Exp $
  * 
  * AEMB Register File
  * Copyright (C) 2006 Shawn Tan Ser Ngiap <address@hidden>
@@ -25,6 +25,10 @@
  *
  * HISTORY
  * $Log: aeMB_regfile.v,v $
+ * Revision 1.8  2007/04/12 20:21:33  sybreon
+ * Moved testbench into /sim/verilog.
+ * Simulation cleanups.
+ *
  * Revision 1.7  2007/04/11 16:30:06  sybreon
  * Cosmetic changes
  *
@@ -417,10 +421,6 @@
       end
    end
    
-   always @(negedge nclk) begin
-      if ((fWE & (rRD_== 5'd0)) || (fLNK & (rRD_== 5'd0)) || (fLD & (rRD_== 
5'd0))) $displayh("!!! Warning: Write to R0 !!!");
-   end
-   
 endmodule // aeMB_regfile
 
 

Modified: gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Entries        
2007-04-16 03:17:59 UTC (rev 5013)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Entries        
2007-04-16 03:18:49 UTC (rev 5014)
@@ -1,3 +1,3 @@
-/cversim/1.1/Fri Mar  9 17:41:55 2007//
 /iversim/1.1/Fri Mar  9 17:41:55 2007//
-D
+/cversim/1.2/Sat Apr 14 06:52:57 2007//
+D/verilog////

Modified: gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/cversim
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/cversim    
2007-04-16 03:17:59 UTC (rev 5013)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/cversim    
2007-04-16 03:18:49 UTC (rev 5014)
@@ -1,7 +1,11 @@
 #!/bin/sh
-# $Id: cversim,v 1.1 2007/03/09 17:41:55 sybreon Exp $
+# $Id: cversim,v 1.2 2007/04/12 20:21:33 sybreon Exp $
 # $Log: cversim,v $
+# Revision 1.2  2007/04/12 20:21:33  sybreon
+# Moved testbench into /sim/verilog.
+# Simulation cleanups.
+#
 # Revision 1.1  2007/03/09 17:41:55  sybreon
 # initial import
 #
-cver $@ ../rtl/verilog/*.v
+cver -q -w $@ ../rtl/verilog/*.v