[Commit-gnuradio] r5017 - in gnuradio/branches/developers/jcorgan/atr: gr-usrp/src usrp/firmware/include usrp/fpga/rbf/rev2 usrp/fpga/rbf/rev4 usrp/fpga/sdr_lib usrp/fpga/toplevel/usrp_std

[jcorgan]

Author: jcorgan
Date: 2007-04-16 12:07:47 -0600 (Mon, 16 Apr 2007)
New Revision: 5017

Added:
   gnuradio/branches/developers/jcorgan/atr/usrp/fpga/sdr_lib/atr_delay.v
Modified:
   gnuradio/branches/developers/jcorgan/atr/gr-usrp/src/db_base.py
   
gnuradio/branches/developers/jcorgan/atr/usrp/firmware/include/fpga_regs_standard.h
   
gnuradio/branches/developers/jcorgan/atr/usrp/firmware/include/fpga_regs_standard.v
   gnuradio/branches/developers/jcorgan/atr/usrp/fpga/rbf/rev2/std_2rxhb_2tx.rbf
   gnuradio/branches/developers/jcorgan/atr/usrp/fpga/rbf/rev4/std_2rxhb_2tx.rbf
   gnuradio/branches/developers/jcorgan/atr/usrp/fpga/sdr_lib/master_control.v
   
gnuradio/branches/developers/jcorgan/atr/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
Log:
Adds capability to independently delay the Auto T/R switching signal
by a configurable number of clock ticks, to allow users to precisely
align their T/R output with the pipeline delays in the transmitter.

There are two new registers:

FR_ATR_TX_DELAY (7'd50)
FR_ATR_RX_DELAY (7'd51)

...and the corresponding db_base.py methods to set them:

db_base.set_atr_tx_delay(clock_ticks)
db_base.set_atr_rx_delay(clock_ticks)

The FPGA synthesis for the 2 RXHB, 2 TX case expands from 95% to 96%,
with no additional synthesis messages or impact on timing.

This has been lightly tested with no problems found. However, it
may be desirable to change the implementation from 32-bit to 16-bit to
save on register space, if we can live with a maximum delay of ~1 ms.



Modified: gnuradio/branches/developers/jcorgan/atr/gr-usrp/src/db_base.py
===================================================================
--- gnuradio/branches/developers/jcorgan/atr/gr-usrp/src/db_base.py     
2007-04-16 03:19:54 UTC (rev 5016)
+++ gnuradio/branches/developers/jcorgan/atr/gr-usrp/src/db_base.py     
2007-04-16 18:07:47 UTC (rev 5017)
@@ -154,6 +154,20 @@
         """
         return self._u._write_fpga_reg(FR_ATR_RXVAL_0 + 3 * self._slot, v)
 
+    def set_atr_tx_delay(self, v):
+       """
+       Set Auto T/R delay (in clock ticks) from when Tx fifo gets data to 
+       when T/R switches.
+       """
+       return self._u._write_fpga_reg(FR_ATR_TX_DELAY, v)
+       
+    def set_atr_rx_delay(self, v):
+       """
+       Set Auto T/R delay (in clock ticks) from when Tx fifo goes empty to 
+       when T/R switches.
+       """
+       return self._u._write_fpga_reg(FR_ATR_RX_DELAY, v)
+       
     # derived classes should override the following methods
 
     def freq_range(self):

Modified: 
gnuradio/branches/developers/jcorgan/atr/usrp/firmware/include/fpga_regs_standard.h
===================================================================
--- 
gnuradio/branches/developers/jcorgan/atr/usrp/firmware/include/fpga_regs_standard.h
 2007-04-16 03:19:54 UTC (rev 5016)
+++ 
gnuradio/branches/developers/jcorgan/atr/usrp/firmware/include/fpga_regs_standard.h
 2007-04-16 18:07:47 UTC (rev 5017)
@@ -181,8 +181,12 @@
 // Possible future values of WIDTH = {4, 2, 1}
 // 12 takes a bit more work, since we need to know packet alignment.
 
+// Clock ticks to delay auto T/R state transitions
+#define FR_ATR_TX_DELAY 50
+#define FR_ATR_RX_DELAY 51
+
 // ------------------------------------------------------------------------
-// FIXME register numbers 50 to 63 are available
+// FIXME register numbers 52 to 63 are available
 
 // ------------------------------------------------------------------------
 // Registers 64 to 79 are reserved for user custom FPGA builds.

Modified: 
gnuradio/branches/developers/jcorgan/atr/usrp/firmware/include/fpga_regs_standard.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/atr/usrp/firmware/include/fpga_regs_standard.v
 2007-04-16 03:19:54 UTC (rev 5016)
+++ 
gnuradio/branches/developers/jcorgan/atr/usrp/firmware/include/fpga_regs_standard.v
 2007-04-16 18:07:47 UTC (rev 5017)
@@ -153,8 +153,12 @@
 // Possible future values of WIDTH = {4, 2, 1}
 // 12 takes a bit more work, since we need to know packet alignment.
 
+// Clock ticks to delay auto T/R state transitions
+`define FR_ATR_TX_DELAY           7'd50
+`define FR_ATR_RX_DELAY           7'd51
+
 // ------------------------------------------------------------------------
-// FIXME register numbers 50 to 63 are available
+// FIXME register numbers 52 to 63 are available
 
 // ------------------------------------------------------------------------
 // Registers 64 to 79 are reserved for user custom FPGA builds.

Modified: 
gnuradio/branches/developers/jcorgan/atr/usrp/fpga/rbf/rev2/std_2rxhb_2tx.rbf
===================================================================
(Binary files differ)

Modified: 
gnuradio/branches/developers/jcorgan/atr/usrp/fpga/rbf/rev4/std_2rxhb_2tx.rbf
===================================================================
(Binary files differ)

Added: gnuradio/branches/developers/jcorgan/atr/usrp/fpga/sdr_lib/atr_delay.v
===================================================================
--- gnuradio/branches/developers/jcorgan/atr/usrp/fpga/sdr_lib/atr_delay.v      
                        (rev 0)
+++ gnuradio/branches/developers/jcorgan/atr/usrp/fpga/sdr_lib/atr_delay.v      
2007-04-16 18:07:47 UTC (rev 5017)
@@ -0,0 +1,83 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2007 Corgan Enterprises LLC
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o);
+   input        clk_i;
+   input        rst_i;
+   input        ena_i;
+   input        tx_empty_i;
+   input [31:0] tx_delay_i;
+   input [31:0] rx_delay_i;
+   output       atr_tx_o;
+
+   reg [3:0]   state;
+   reg [31:0]  count;
+
+   `define ST_RX_DELAY 4'b0001
+   `define ST_RX       4'b0010
+   `define ST_TX_DELAY 4'b0100
+   `define ST_TX       4'b1000
+
+   always @(posedge clk_i)
+     if (rst_i | ~ena_i)
+       begin
+         state <= `ST_RX;
+         count <= 0;
+       end
+     else
+       case (state)
+        `ST_RX:
+          if (!tx_empty_i)
+            begin
+               state <= `ST_TX_DELAY;
+               count <= tx_delay_i;
+            end
+
+        `ST_TX_DELAY:
+          if (count == 0)
+            state <= `ST_TX;
+          else
+            count = count - 1;
+
+        `ST_TX:
+          if (tx_empty_i)
+            begin
+               state <= `ST_RX_DELAY;
+               count <= rx_delay_i;
+            end
+
+        `ST_RX_DELAY:
+          if (count == 0)
+            state <= `ST_RX;
+          else
+            count = count - 1;
+        
+        default:               // Error
+          begin
+             state <= `ST_RX;
+             count <= 0;
+          end
+       endcase
+   
+   assign atr_tx_o = state[3] | state[0];
+   
+endmodule // atr_delay
+

Modified: 
gnuradio/branches/developers/jcorgan/atr/usrp/fpga/sdr_lib/master_control.v
===================================================================
--- gnuradio/branches/developers/jcorgan/atr/usrp/fpga/sdr_lib/master_control.v 
2007-04-16 03:19:54 UTC (rev 5016)
+++ gnuradio/branches/developers/jcorgan/atr/usrp/fpga/sdr_lib/master_control.v 
2007-04-16 18:07:47 UTC (rev 5017)
@@ -3,6 +3,7 @@
 //  USRP - Universal Software Radio Peripheral
 //
 //  Copyright (C) 2003,2005 Matt Ettus
+//  Copyright (C) 2007 Corgan Enterprises LLC
 //
 //  This program is free software; you can redistribute it and/or modify
 //  it under the terms of the GNU General Public License as published by
@@ -111,8 +112,9 @@
           <= #1 (io_3_reg & ~serial_data[31:16]) | (serial_data[15:0] & 
serial_data[31:16] );
        endcase // case(serial_addr)
 
-   wire        transmit_now = !tx_empty & enable_tx;
+   wire        transmit_now;
    wire        atr_ctl;
+   wire [31:0] atr_tx_delay, atr_rx_delay;
    wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, 
atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, 
atr_rxval_3;
       
    setting_reg #(`FR_ATR_MASK_0) 
sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0));
@@ -132,8 +134,14 @@
    setting_reg #(`FR_ATR_RXVAL_3) 
sr_atr_rxval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_3));
 
    //setting_reg #(`FR_ATR_CTL) 
sr_atr_ctl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_ctl));
+   setting_reg #(`FR_ATR_TX_DELAY) 
sr_atr_tx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_tx_delay));
+   setting_reg #(`FR_ATR_RX_DELAY) 
sr_atr_rx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rx_delay));
+
    assign      atr_ctl = 1'b1;
 
+   atr_delay atr_delay(.clk_i(master_clk),.rst_i(tx_dsp_reset),.ena_i(atr_ctl 
& enable_tx),.tx_empty_i(tx_empty),
+                      
.tx_delay_i(atr_tx_delay),.rx_delay_i(atr_rx_delay),.atr_tx_o(transmit_now));
+   
    wire [15:0] atr_selected_0 = transmit_now ? atr_txval_0 : atr_rxval_0;
    wire [15:0] io_0 = ({{16{atr_ctl}}} &  atr_mask_0 & atr_selected_0) | 
(~({{16{atr_ctl}}} & atr_mask_0) & io_0_reg);
    

Modified: 
gnuradio/branches/developers/jcorgan/atr/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
===================================================================
--- 
gnuradio/branches/developers/jcorgan/atr/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
   2007-04-16 03:19:54 UTC (rev 5016)
+++ 
gnuradio/branches/developers/jcorgan/atr/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
   2007-04-16 18:07:47 UTC (rev 5017)
@@ -27,7 +27,7 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04  JULY 13, 
2003"
-set_global_assignment -name LAST_QUARTUS_VERSION 6.1
+set_global_assignment -name LAST_QUARTUS_VERSION 7.0
 
 # Pin & Location Assignments
 # ==========================
@@ -368,6 +368,9 @@
 # end ENTITY(usrp_std)
 # --------------------
 
+set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition 
-to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v