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[Commit-gnuradio] r5077 - gnuradio/branches/developers/matt/u2f/boot_cpl
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From: |
matt |
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Subject: |
[Commit-gnuradio] r5077 - gnuradio/branches/developers/matt/u2f/boot_cpld |
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Date: |
Sun, 22 Apr 2007 17:32:03 -0600 (MDT) |
Author: matt
Date: 2007-04-22 17:32:03 -0600 (Sun, 22 Apr 2007)
New Revision: 5077
Modified:
gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.ise
gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.lfp
gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.ucf
gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.v
Log:
modified for ram loader
Modified: gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.ise
===================================================================
(Binary files differ)
Modified: gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.lfp
===================================================================
--- gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.lfp
2007-04-22 22:42:26 UTC (rev 5076)
+++ gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.lfp
2007-04-22 23:32:03 UTC (rev 5077)
@@ -0,0 +1,5 @@
+# begin LFP file C:\cygwin\home\matt\u2f\boot_cpld\boot_cpld.lfp
+designfile boot_cpld.v
+parttype xc9572xl-vq44-10
+bus_delimiter 0;
+set_busdelim_onsave 1;
Modified: gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.ucf
===================================================================
--- gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.ucf
2007-04-22 22:42:26 UTC (rev 5076)
+++ gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.ucf
2007-04-22 23:32:03 UTC (rev 5077)
@@ -8,31 +8,31 @@
NET "CFG_PROG_B" LOC = "P39" ;
NET "CLK_25MHZ" LOC = "P5" ;
NET "CLK_25MHZ_EN" LOC = "P6" ;
-NET "DEBUG[0]" LOC = "P43" ;
-NET "DEBUG[10]" LOC = "P34" ;
-NET "DEBUG[1]" LOC = "P44" ;
-NET "DEBUG[2]" LOC = "P1" ;
-NET "DEBUG[3]" LOC = "P2" ;
-NET "DEBUG[4]" LOC = "P3" ;
-NET "DEBUG[5]" LOC = "P29" ;
-NET "DEBUG[6]" LOC = "P30" ;
-NET "DEBUG[7]" LOC = "P31" ;
-NET "DEBUG[8]" LOC = "P32" ;
-NET "DEBUG[9]" LOC = "P33" ;
-NET "LED[0]" LOC = "P12" ;
-NET "LED[1]" LOC = "P8" ;
-NET "LED[2]" LOC = "P7" ;
+NET "CPLD_CLK" LOC = "P13" ;
+NET "DEBUG<0>" LOC = "P43" ;
+NET "DEBUG<10>" LOC = "P34" ;
+NET "DEBUG<1>" LOC = "P44" ;
+NET "DEBUG<2>" LOC = "P1" ;
+NET "DEBUG<3>" LOC = "P2" ;
+NET "DEBUG<4>" LOC = "P3" ;
+NET "DEBUG<5>" LOC = "P29" ;
+NET "DEBUG<6>" LOC = "P30" ;
+NET "DEBUG<7>" LOC = "P31" ;
+NET "DEBUG<8>" LOC = "P32" ;
+NET "DEBUG<9>" LOC = "P33" ;
+NET "DONE" LOC = "P16" ;
+NET "LED<0>" LOC = "P12" ;
+NET "LED<1>" LOC = "P8" ;
+NET "LED<2>" LOC = "P7" ;
+NET "MODE" LOC = "P18" ;
NET "POR" LOC = "P42" ;
-NET "SD_CLK" LOC = "P22" ;
+NET "SD_CLK" LOC = "P22" ;
NET "SD_DAT1" LOC = "P27" ;
NET "SD_DAT2" LOC = "P28" ;
NET "SD_Din" LOC = "P21" ;
NET "SD_Dout" LOC = "P23" ;
NET "SD_nCS" LOC = "P20" ;
-NET "SPI_CPLD_CLK" LOC = "P13" ;
-NET "SPI_CPLD_DIN" LOC = "P14" ;
-NET "SPI_CPLD_DOUT" LOC = "P18" ;
-NET "SPI_CPLD_EN" LOC = "P16" ;
+NET "START" LOC = "P14" ;
#PACE: Start of PACE Area Constraints
Modified: gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.v 2007-04-22
22:42:26 UTC (rev 5076)
+++ gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.v 2007-04-22
23:32:03 UTC (rev 5077)
@@ -19,7 +19,7 @@
//
//////////////////////////////////////////////////////////////////////////////////
module boot_cpld
- (CLK_25MHZ, CLK_25MHZ_EN, LED, SPI_CPLD_CLK, SPI_CPLD_DIN, SPI_CPLD_DOUT,
SPI_CPLD_EN,
+ (CLK_25MHZ, CLK_25MHZ_EN, LED, CPLD_CLK, START, MODE, DONE,
SD_nCS, SD_Din, SD_CLK, SD_Dout, SD_DAT1, SD_DAT2, CFG_INIT_B, CFG_Din,
DEBUG, POR,
CFG_CCLK, CFG_DONE, CFG_PROG_B);
@@ -28,13 +28,7 @@
output [2:0] LED;
output [10:0] DEBUG;
input POR;
-
- // To FPGA data interface
- output SPI_CPLD_CLK; // temporary, for clock bootstrapping
- input SPI_CPLD_DIN;
- input SPI_CPLD_DOUT;
- input SPI_CPLD_EN;
-
+
// To SD Card
output SD_nCS;
output SD_Din;
@@ -45,36 +39,40 @@
// To FPGA Config Interface
input CFG_INIT_B;
- output CFG_Din;
+ output CFG_Din; // Also used in Data interface
output CFG_CCLK;
input CFG_DONE;
output CFG_PROG_B;
-
+
+ // To FPGA data interface
+ output CPLD_CLK;
+ input START;
+ input MODE;
+ input DONE;
+
assign CLK_25MHZ_EN = 1'b1;
assign LED[0] = ~CFG_DONE;
assign LED[1] = CFG_INIT_B;
- assign LED[2] = CFG_PROG_B;
-
- assign SPI_CPLD_CLK = CLK_25MHZ;
+ assign LED[2] = ~CFG_PROG_B;
+
+ reg which_clock;
+ always @(negedge POR or negedge CLK_25MHZ)
+ if(~POR)
+ which_clock <= #1 1'b0;
+ else if(DONE)
+ which_clock <= #1 1'b1;
+
+ assign CPLD_CLK = which_clock ? CLK_25MHZ : CFG_CCLK;
- wire start, mode, detached, dat_done, en_outs;
+ wire en_outs;
wire [3:0] set_sel = 4'd0;
-
- assign DEBUG = { /* start, mode, */ detached, dat_done,
+
+ assign DEBUG = { /* MODE */ START, DONE,
SD_CLK, SD_nCS, SD_Dout, SD_Din,
- CFG_PROG_B, CFG_INIT_B, CFG_DONE, CFG_CCLK,
CFG_Din};
-
- // Control signals, need to figure out how to drive these
- //assign start = SPI_CPLD_DOUT; // This is the important one
- //assign dat_done = SPI_CPLD_DIN;
- //assign mode = SPI_CPLD_EN;
-
- assign start = 1'b1; //SPI_CPLD_DOUT; // This is the important one
- assign dat_done = 1'b0; //SPI_CPLD_DIN;
- assign mode = 1'b0; //SPI_CPLD_EN;
-
+ CFG_PROG_B, CFG_INIT_B, CFG_DONE, CPLD_CLK,
CFG_Din};
+
spi_boot #(.width_set_sel_g(4), // How many sets (16)
.width_bit_cnt_g(6), // Block length (12 is faster, 6 is minimum)
.width_img_cnt_g(2), // How many images per set
@@ -95,10 +93,10 @@
.spi_en_outs_o(en_outs),
// Data Port
- .start_i(start),
- .mode_i(mode), // 0->conf mode, 1->data mode
+ .start_i(START),
+ .mode_i(MODE), // 0->conf mode, 1->data mode
.detached_o(detached),
- .dat_done_i(dat_done),
+ .dat_done_i(DONE),
.set_sel_i(set_sel),
// To FPGA
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