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[Commit-gnuradio] r5084 - gnuradio/branches/developers/matt/u2f/control_
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From: |
matt |
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Subject: |
[Commit-gnuradio] r5084 - gnuradio/branches/developers/matt/u2f/control_lib |
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Date: |
Mon, 23 Apr 2007 13:02:59 -0600 (MDT) |
Author: matt
Date: 2007-04-23 13:02:59 -0600 (Mon, 23 Apr 2007)
New Revision: 5084
Added:
gnuradio/branches/developers/matt/u2f/control_lib/WB_SIM.sav
gnuradio/branches/developers/matt/u2f/control_lib/bootrom.mem
gnuradio/branches/developers/matt/u2f/control_lib/ram_loader.v
gnuradio/branches/developers/matt/u2f/control_lib/spi.v
Log:
misc stuff, some may be removed soon
Added: gnuradio/branches/developers/matt/u2f/control_lib/WB_SIM.sav
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/WB_SIM.sav
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/WB_SIM.sav
2007-04-23 19:02:59 UTC (rev 5084)
@@ -0,0 +1,47 @@
+[size] 1400 971
+[pos] -1 -1
+*-6.099828 350 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 -1
address@hidden
+wb_sim.wb_rst
+wb_sim.wb_clk
address@hidden
+wb_sim.rom_data[47:0]
address@hidden
+wb_sim.rom_addr[15:0]
address@hidden
+wb_sim.start
+wb_sim.wb_ack
address@hidden
+wb_sim.wb_adr[15:0]
address@hidden
+wb_sim.wb_cyc
address@hidden
+wb_sim.wb_dat[31:0]
+wb_sim.wb_sel[3:0]
address@hidden
+wb_sim.wb_stb
+wb_sim.wb_we
address@hidden
+wb_sim.port_output[31:0]
address@hidden
+wb_sim.system_control.POR
+wb_sim.system_control.aux_clk
+wb_sim.system_control.clk_fpga
address@hidden
+wb_sim.system_control.done
address@hidden
+wb_sim.system_control.dsp_clk
+wb_sim.system_control.fin_del1
+wb_sim.system_control.fin_del2
+wb_sim.system_control.fin_del3
+wb_sim.system_control.fin_ret_aux
address@hidden
+wb_sim.system_control.fin_ret_fpga
address@hidden
+wb_sim.system_control.finished
+wb_sim.system_control.reset_out
+wb_sim.system_control.start
+wb_sim.system_control.started
+wb_sim.system_control.wb_clk_o
+wb_sim.system_control.wb_rst_o
+wb_sim.system_control.wb_rst_o_alt
Added: gnuradio/branches/developers/matt/u2f/control_lib/bootrom.mem
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/bootrom.mem
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/bootrom.mem
2007-04-23 19:02:59 UTC (rev 5084)
@@ -0,0 +1,26 @@
+00000C000F03
+101400000000
+ // SPI: Set Divider to div by 2
+// Both clk sel choose ext ref (0), both are enabled (1), turn off SERDES,
ADCs, turn on leds
+1018_0000_0001 // SPI: Choose AD9510
+1010_0000_3418 // SPI: Auto-slave select, interrupt when done, TX_NEG,
24-bit word
+1000_0000_0010 // SPI: AD9510 A:0 D:10 Set up AD9510 SPI
+1010_0000_3518 // SPI: SEND IT Auto-slave select, interrupt when done,
TX_NEG, 24-bit word
+ffff_ffff_ffff // terminate
+#// First 16 bits are address, last 32 are data
+#// First 4 bits of address select which slave
+// 6'd01 : addr_data = {13'h45,8'h00}; // CLK2 drives
distribution, everything on
+// 6'd02 : addr_data = {13'h3D,8'h80}; // Turn on output 1,
normal levels
+// 6'd03 : addr_data = {13'h4B,8'h80}; // Bypass divider 1 (div
by 1)
+// 6'd04 : addr_data = {13'h08,8'h47}; // POS PFD, Dig LK Det,
Charge Pump normal
+// 6'd05 : addr_data = {13'h09,8'h70}; // Max Charge Pump
current
+// 6'd06 : addr_data = {13'h0A,8'h04}; // Normal operation,
Prescalar Div by 2, PLL On
+// 6'd07 : addr_data = {13'h0B,8'h00}; // RDIV MSB (6 bits)
+// 6'd08 : addr_data = {13'h0C,8'h01}; // RDIV LSB (8 bits),
Div by 1
+// 6'd09 : addr_data = {13'h0D,8'h00}; // Everything normal,
Dig Lock Det
+// 6'd10 : addr_data = {13'h07,8'h00}; // Disable LOR detect -
LOR causes failure...
+// 6'd11 : addr_data = {13'h04,8'h00}; // A Counter = Don't
Care
+// 6'd12 : addr_data = {13'h05,8'h00}; // B Counter MSB = 0
+// 6'd13 : addr_data = {13'h06,8'h05}; // B Counter LSB = 5
+ // default : addr_data = {13'h5A,8'h01}; // Register Update
+// @ 55 // Jump to new address 8'h55
Added: gnuradio/branches/developers/matt/u2f/control_lib/ram_loader.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/ram_loader.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/ram_loader.v
2007-04-23 19:02:59 UTC (rev 5084)
@@ -0,0 +1,184 @@
+
+
+module ram_loader (input clk_i, input reset_i,
+ input cfg_clk_i, input cfg_data_i,
+ output start_o, output mode_o, output done_o,
+ input detached_i,
+ output [11:0] ram_addr,
+ output [7:0] ram_data,
+ output ram_we);
+
+ // FSM to control start signal, clocked on main clock
+`define FSM1_WAIT_DETACH 2'b00
+`define FSM1_CHECK_NO_DONE 2'b01
+`define FSM1_WAIT_DONE 2'b10
+
+ reg [1:0] start_fsm_q, start_fsm_s;
+ reg start_q, enable_q, start_s, enable_s;
+ reg done_q, done_s;
+
+ always @(posedge clk_i or posedge reset_i)
+ if(reset_i)
+ begin
+ start_fsm_q <= #1 `FSM1_WAIT_DETACH;
+ start_q <= #1 1'b0;
+ enable_q <= #1 1'b0;
+ end
+ else
+ begin
+ start_fsm_q <= #1 start_fsm_s;
+ enable_q <= #1 enable_s;
+ start_q <= #1 start_s;
+ end // else: !if(reset_i)
+
+ always @*
+ case(start_fsm_q)
+ `FSM1_WAIT_DETACH:
+ if(detached_i == 1'b1)
+ begin
+ start_fsm_s <= `FSM1_CHECK_NO_DONE;
+ enable_s <= 1'b1;
+ start_s <= 1'b1;
+ end
+ else
+ begin
+ start_fsm_s <= `FSM1_WAIT_DETACH;
+ enable_s <= enable_q;
+ start_s <= start_q;
+ end // else: !if(detached_i == 1'b1)
+ `FSM1_CHECK_NO_DONE:
+ if(~done_q)
+ begin
+ start_fsm_s <= `FSM1_WAIT_DONE;
+ enable_s <= enable_q;
+ start_s <= start_q;
+ end
+ else
+ begin
+ start_fsm_s <= `FSM1_CHECK_NO_DONE;
+ enable_s <= enable_q;
+ start_s <= start_q;
+ end // else: !if(~done_q)
+ `FSM1_WAIT_DONE:
+ if(done_q)
+ begin
+ start_fsm_s <= `FSM1_WAIT_DETACH;
+ enable_s <= 1'b0;
+ start_s <= 1'b0;
+ end
+ else
+ begin
+ start_fsm_s <= `FSM1_WAIT_DONE;
+ enable_s <= enable_q;
+ start_s <= start_q;
+ end // else: !if(done_q)
+ default:
+ begin
+ start_fsm_s <= `FSM1_WAIT_DETACH;
+ enable_s <= enable_q;
+ start_s <= start_q;
+ end // else: !if(done_q)
+ endcase // case(start_fsm_q)
+
+
+
+// FSM running on data clock
+
+`define FSM2_IDLE 3'b000
+`define FSM2_WE_ON 3'b001
+`define FSM2_WE_OFF 3'b010
+`define FSM2_INC_ADDR1 3'b011
+`define FSM2_INC_ADDR2 3'b100
+`define FSM2_FINISHED 3'b101
+
+ reg [11:0] addr_q;
+ reg [7:0] shift_dat_q, ser_dat_q;
+ reg [2:0] bit_q, fsm_q, fsm_s;
+ reg bit_ovfl_q, ram_we_s, ram_we_q, mode_q, mode_s,
inc_addr_s;
+
+ always @(posedge cfg_clk_i or posedge reset_i)
+ if(reset_i)
+ begin
+ addr_q <= #1 12'd0;
+ shift_dat_q <= #1 8'd0;
+ ser_dat_q <= #1 8'd0;
+ bit_q <= #1 3'd0;
+ bit_ovfl_q <= #1 1'b0;
+ fsm_q <= #1 `FSM2_IDLE;
+ ram_we_q <= #1 1'b0;
+ done_q <= #1 1'b0;
+ mode_q <= #1 1'b0;
+ end
+ else
+ begin
+ if(inc_addr_s)
+ addr_q <= #1 addr_q + 12'd1;
+ if(enable_q)
+ begin
+ bit_q <= #1 bit_q + 1;
+ bit_ovfl_q <= #1 (bit_q == 3'd7);
+ shift_dat_q[0] <= #1 cfg_data_i;
+ shift_dat_q[7:1] <= #1 shift_dat_q[6:0];
+ end
+ if(bit_ovfl_q)
+ ser_dat_q <= #1 shift_dat_q;
+
+ fsm_q <= #1 fsm_s;
+
+ ram_we_q <= #1 ram_we_s;
+
+ if(done_s)
+ done_q <= #1 1'b1;
+ mode_q <= mode_s;
+ end // else: !if(reset_i)
+
+ always @*
+ begin
+ inc_addr_s <= 1'b0;
+ ram_we_s <= 1'b0;
+ done_s <= 1'b0;
+ fsm_s <= `FSM2_IDLE;
+ mode_s <= 1'b0;
+
+ case(fsm_q)
+ `FSM2_IDLE :
+ if(start_q)
+ if(bit_ovfl_q)
+ fsm_s <= `FSM2_WE_ON;
+ `FSM2_WE_ON:
+ begin
+ ram_we_s <= 1'b1;
+ fsm_s <= `FSM2_WE_OFF;
+ end
+ `FSM2_WE_OFF:
+ fsm_s <= `FSM2_INC_ADDR1;
+ `FSM2_INC_ADDR1:
+ fsm_s <= `FSM2_INC_ADDR2;
+ `FSM2_INC_ADDR2:
+ if(addr_q == 12'h3FF)
+ begin
+ fsm_s <= `FSM2_FINISHED;
+ done_s <= 1'b1;
+ mode_s <= 1'b1;
+ end
+ else
+ begin
+ inc_addr_s <= 1'b1;
+ fsm_s <= `FSM2_IDLE;
+ end // else: !if(addr_q == 12'h0FF)
+ `FSM2_FINISHED:
+ begin
+ fsm_s <= `FSM2_FINISHED;
+ mode_s <= 1'b1;
+ end
+ endcase // case(fsm_q)
+ end // always @ *
+
+ assign start_o = start_q;
+ assign mode_o = mode_q;
+ assign done_o = start_q ? done_q : 1'b1;
+ assign ram_addr = addr_q;
+ assign ram_data = ser_dat_q;
+ assign ram_we = ram_we_q;
+
+endmodule // ram_loader
Added: gnuradio/branches/developers/matt/u2f/control_lib/spi.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/spi.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/spi.v 2007-04-23
19:02:59 UTC (rev 5084)
@@ -0,0 +1,84 @@
+
+
+// AD9510 Register Map (from datasheet Rev. A)
+
+/* INSTRUCTION word format (16 bits)
+ * 15 Read = 1, Write = 0
+ * 14:13 W1/W0, Number of bytes 00 - 1, 01 - 2, 10 - 3, 11 - stream
+ * 12:0 Address
+ */
+
+/* ADDR Contents Value (hex)
+ * 00 Serial Config Port 10 (def) -- MSB first, SDI/SDO separate
+ * 04 A Counter
+ * 05-06 B Counter
+ * 07-0A PLL Control
+ * 0B-0C R Divider
+ * 0D PLL Control
+ * 34-3A Fine Delay
+ * 3C-3F LVPECL Outs
+ * 40-43 LVDS/CMOS Outs
+ * 45 Clock select, power down
+ * 48-57 Dividers
+ * 58 Func and Sync
+ * 5A Update regs
+ */
+
+
+module spi
+ (input reset,
+ input clk,
+
+ // SPI signals
+ output sen,
+ output sclk,
+ input sdi,
+ output sdo,
+
+ // Interfaces
+ input read_1,
+ input write_1,
+ input [15:0] command_1,
+ input [15:0] wdata_1,
+ output [15:0] rdata_1,
+ output reg done_1,
+ input msb_first_1,
+ input [5:0] command_width_1,
+ input [5:0] data_width_1,
+ input [7:0] clkdiv_1
+
+ );
+
+ reg [15:0] command, wdata, rdata;
+ reg done;
+
+ always @(posedge clk)
+ if(reset)
+ done_1 <= #1 1'b0;
+
+ always @(posedge clk)
+ if(reset)
+ begin
+ counter <= #1 7'd0;
+ command <= #1 20'd0;
+ end
+ else if(start)
+ begin
+ counter <= #1 7'd1;
+ command <= #1 {read,w,addr_data};
+ end
+ else if( |counter && ~done )
+ begin
+ counter <= #1 counter + 7'd1;
+ if(~counter[0])
+ command <= {command[22:0],1'b0};
+ end
+
+ wire done = (counter == 8'd49);
+
+ assign sen = (done | counter == 8'd0); // CSB is high when we're not doing
anything
+ assign sclk = ~counter[0];
+ assign sdo = command[23];
+
+
+endmodule // clock_control
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