[Commit-gnuradio] r5092 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations

[thottelt]

Author: thottelt
Date: 2007-04-23 17:10:38 -0600 (Mon, 23 Apr 2007)
New Revision: 5092

Added:
   gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
   gnuradio/branches/developers/thottelt/simulations/packets.dat
Modified:
   
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
   
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
   
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo.v
   gnuradio/branches/developers/thottelt/simulations/tx.mpf
   gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
   gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo_test.v
Log:
added have_space to fifo and fake_fx2 skeleton

Modified: 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
===================================================================
--- 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
        2007-04-23 20:40:04 UTC (rev 5091)
+++ 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
        2007-04-23 23:10:38 UTC (rev 5092)
@@ -3,6 +3,7 @@
     input       clock,
     input       [15:0]ram_data_in,
     input       write_enable,
+    output  reg have_space,
     output  reg [15:0]ram_data_out,
     output  reg pkt_waiting,
     input       read_enable,
@@ -24,6 +25,7 @@
 
     wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
     wire [7-2+NUM_PACKETS:0] usb_ram_ain ;
+    reg isfull;
 
     assign usb_ram_aout = {usb_ram_packet_out, usb_ram_offset_out} ;
     assign usb_ram_ain = {usb_ram_packet_in, usb_ram_offset_in} ;
@@ -39,6 +41,19 @@
             pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 
256;
     end
 
+    // Check if there is room
+    always @(usb_ram_ain, usb_ram_aout)
+    begin
+        if (reset)
+            have_space <= 1;
+        else if (usb_ram_ain == usb_ram_aout)
+            have_space <= ~isfull;   
+        else if (usb_ram_ain > usb_ram_aout)
+            have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 
1);
+        else
+            have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
+    end
+
     /* RAM Write Address process */
     always @(posedge clock)
     begin
@@ -62,6 +77,8 @@
                   end
                 else
                     usb_ram_offset_in <= usb_ram_offset_in + 1 ;
+                    if (usb_ram_ain + 1 == usb_ram_aout)
+                       isfull <= 1;
               end
     end
 
@@ -81,6 +98,7 @@
           begin
             usb_ram_packet_out <= 0 ;
             usb_ram_offset_out <= 0 ;
+            isfull <= 0;
           end
         else
             if( skip_packet )
@@ -96,7 +114,9 @@
                   end
                 else
                     usb_ram_offset_out <= usb_ram_offset_out + 1 ;  
-            end                     
+            end 
+            if (usb_ram_ain == usb_ram_aout)
+               isfull <= 0;                    
     end
 
     /* RAM Reading Process */

Modified: 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
--- 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
        2007-04-23 20:40:04 UTC (rev 5091)
+++ 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
        2007-04-23 23:10:38 UTC (rev 5092)
@@ -1,28 +1,3 @@
-// -*- verilog -*-
-//
-//  USRP - Universal Software Radio Peripheral
-//
-//  Copyright (C) 2003 Matt Ettus
-//
-//  This program is free software; you can redistribute it and/or modify
-//  it under the terms of the GNU General Public License as published by
-//  the Free Software Foundation; either version 2 of the License, or
-//  (at your option) any later version.
-//
-//  This program is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-//  GNU General Public License for more details.
-//
-//  You should have received a copy of the GNU General Public License
-//  along with this program; if not, write to the Free Software
-//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
-//
-
-// Interface to Cypress FX2 bus
-// A packet is 512 Bytes.  Each fifo line is 2 bytes
-// Fifo has 1024 or 2048 lines
-
 module tx_buffer_inband
   ( input usbclk,
     input bus_reset,  // Used here for the 257-Hack to fix the FX2 bug
@@ -49,8 +24,6 @@
     );
 
    wire [15:0] tx_data_bus;
-   //TODO: increment it
-   reg [31:0] time_counter;
 
    wire WR_chan_0;
    wire chan_0_done;
@@ -66,10 +39,19 @@
    wire WR_cmd;
    wire cmd_done;
    
+   //EXTERNAL REGISTER
+   //TODO: increment it
+   reg [31:0] time_counter;
+   reg [7:0] txstrobe_rate_0;
+   reg [7:0] txstrobe_rate_1;
+   
+   
+   //Usb block
    wire [15:0] tupf_fifodata;
    wire tupf_pkt_waiting;
    wire tupf_rdreq;
    wire tupf_skip;
+   wire tupf_have_space;
    
    usb_packet_fifo tx_usb_packet_fifo 
      (  .reset(reset),
@@ -80,7 +62,8 @@
         .ram_data_out(tupf_fifodata),
         .pkt_waiting(tupf_pkt_waiting),
         .read_enable(tupf_rdreq), 
-        .skip_packet(tupf_skip)
+        .skip_packet(tupf_skip),
+        .have_space(tupf_have_space)
        );
    
        usb_fifo_reader tx_usb_packet_reader (
@@ -99,10 +82,14 @@
       .fifodata(tupf_fifodata)
        );
 
+
+   //Channel 0 block
    wire [15:0] tdpf_fifodata_0;
    wire tdpf_pkt_waiting_0;
    wire tdpf_rdreq_0;
    wire tdpf_skip_0;
+   wire tdpf_have_space_0;
+   wire txstrobe_chan_0;
 
    data_packet_fifo tx_data_packet_fifo_0 
      (  .reset(reset),
@@ -113,13 +100,24 @@
         .pkt_waiting(tdpf_pkt_waiting_0),
         .read_enable(tdpf_rdreq_0),
         .pkt_complete(chan_0_done), 
-        .skip_packet(tdpf_skip_0)
+        .skip_packet(tdpf_skip_0),
+        .have_space(tdpf_have_space_0)
        );
-
+   
+   strobe_gen strobe_gen_0
+    (   .clock(txclk),
+        .reset(reset),
+        .enable(1'b1),
+        .rate(txstrobe_rate_0),
+        .strobe_in(txstrobe),
+        .strobe(txstrobe_chan_0) 
+       );
+   
    chan_fifo_reader tx_chan_0_reader (
       .reset(reset),
       .tx_clock(txclk),
       .tx_strobe(txstrobe),
+      //.tx_strobe(txstrobe_chan_0),
       .adc_clock(time_counter),
       .samples_format(4'b0),
       .tx_q(tx_q_0),
@@ -132,10 +130,14 @@
       .pkt_waiting(tdpf_pkt_waiting_0)
    );  
    
+   
+   //Channel 1 block
    wire [15:0] tdpf_fifodata_1;
    wire tdpf_pkt_waiting_1;
    wire tdpf_rdreq_1;
    wire tdpf_skip_1;
+   wire tdpf_have_space_1;
+   wire txstrobe_chan_1;
    
    data_packet_fifo tx_data_packet_fifo_1 
      (  .reset(reset),
@@ -146,13 +148,24 @@
         .pkt_waiting(tdpf_pkt_waiting_1),
         .read_enable(tdpf_rdreq_1),
         .pkt_complete(chan_1_done), 
-        .skip_packet(tdpf_skip_1)
+        .skip_packet(tdpf_skip_1),
+        .have_space(tdpf_have_space_1)
        );
    
+   strobe_gen strobe_gen_1
+    (   .clock(txclk),
+        .reset(reset),
+        .enable(1'b1),
+        .rate(txstrobe_rate_1),
+        .strobe_in(txstrobe),
+        .strobe(txstrobe_chan_1) 
+       );
+   
    chan_fifo_reader tx_chan_1_reader (
       .reset(reset),
       .tx_clock(txclk),
       .tx_strobe(txstrobe),
+      //.tx_strobe(txstrobe_chan_1),
       .adc_clock(time_counter),
       .samples_format(4'b0),
       .tx_q(tx_q_1),

Modified: 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo.v
===================================================================
--- 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo.v
 2007-04-23 20:40:04 UTC (rev 5091)
+++ 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo.v
 2007-04-23 23:10:38 UTC (rev 5092)
@@ -6,6 +6,7 @@
     input       write_enable,
     output  reg [15:0]ram_data_out,
     output  reg pkt_waiting,
+    output  reg have_space,
     input       read_enable,
     input       skip_packet          ) ;
 
@@ -22,6 +23,7 @@
     reg [1:0] usb_ram_packet ;
 
     wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
+    reg isfull;
 
     assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ;
     
@@ -30,11 +32,26 @@
     begin
         if (reset)
             pkt_waiting <= 0;
-        else if (usb_ram_ain >= usb_ram_aout)
-            pkt_waiting <= usb_ram_ain - usb_ram_aout >= 256;
+        else if (usb_ram_ain == usb_ram_aout)
+            pkt_waiting <= isfull;
+        else if (usb_ram_ain > usb_ram_aout)
+            pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256;
         else
             pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 
256;
     end
+    
+    // Check if there is room
+    always @(usb_ram_ain, usb_ram_aout)
+    begin
+        if (reset)
+            have_space <= 1;
+        else if (usb_ram_ain == usb_ram_aout)
+            have_space <= ~isfull;   
+        else if (usb_ram_ain > usb_ram_aout)
+            have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 
1);
+        else
+            have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
+    end
 
     /* RAM Write Address process */
     always @(posedge clock_in)
@@ -45,6 +62,8 @@
             if( write_enable ) 
               begin
                 usb_ram_ain <= usb_ram_ain + 1 ;
+                if (usb_ram_ain + 1 == usb_ram_aout)
+                   isfull <= 1;
               end
     end
 
@@ -64,6 +83,7 @@
           begin
             usb_ram_packet <= 0 ;
             usb_ram_offset <= 0 ;
+            isfull <= 0;
           end
         else
             if( skip_packet )
@@ -78,7 +98,9 @@
                     usb_ram_packet <= usb_ram_packet + 1 ;
                   end
                 else
-                    usb_ram_offset <= usb_ram_offset + 1 ;                     
  
+                    usb_ram_offset <= usb_ram_offset + 1 ;
+            if (usb_ram_ain == usb_ram_aout)
+               isfull <= 0;                       
     end
 
     /* RAM Reading Process */

Added: gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/fake_fx2.v                
                (rev 0)
+++ gnuradio/branches/developers/thottelt/simulations/fake_fx2.v        
2007-04-23 23:10:38 UTC (rev 5092)
@@ -0,0 +1,50 @@
+module fake_fx2();
+    
+integer file, start, count, r;
+reg [15:0] packet [255:0];
+reg usbclock;
+reg reset;
+reg [7:0] i;
+reg [15:0] usbdata;
+reg have_space;
+
+initial begin
+   file = $fopen("packets.dat", "r");
+   start = 0;
+   count = 0;
+   usbclock = 0;
+   have_space = 0;
+   reset = 1;
+   i = 0;
+   
+   #40 reset = 0;
+   
+   if (file == 0)
+      begin
+          $display("cannot open packets.dat");
+          $finish;
+      end
+
+   while($feof(file) == 0)
+      begin
+         r = $fread(packet, file);
+         if (r != 512)
+            begin
+               $display("error while reading packets.dat");
+               $finish;
+            end
+         
+         repeat (256) begin
+          @(posedge usbclock)
+            usbdata = packet[i];
+            i = i + 1 ;
+        end
+      end
+      
+   $fclose(file);
+end
+
+always
+   #2 usbclock = ~ usbclock;
+    
+endmodule


Property changes on: 
gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
___________________________________________________________________
Name: svn:executable
   + *

Added: gnuradio/branches/developers/thottelt/simulations/packets.dat
===================================================================
(Binary files differ)


Property changes on: 
gnuradio/branches/developers/thottelt/simulations/packets.dat
___________________________________________________________________
Name: svn:mime-type
   + application/octet-stream

Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf    2007-04-23 
20:40:04 UTC (rev 5091)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf    2007-04-23 
23:10:38 UTC (rev 5092)
@@ -243,29 +243,31 @@
 Project_Version = 6
 Project_DefaultLib = work
 Project_SortMethod = unused
-Project_Files_Count = 11
+Project_Files_Count = 12
 Project_File_0 = ./strobe_gen_test.v
 Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177269906 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_1 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177273481 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6 
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_1 = ./fake_fx2.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177369114 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 
cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_2 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
 Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177272423 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 8 
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_3 = ./usb_packet_fifo_test.v
-Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1176487761 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0 
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_4 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177174948 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 5 
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_5 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177194757 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_6 = ./tx_buffer_test.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177194907 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3 
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_7 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177274378 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_8 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
-Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1175362687 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_9 = ./chan_fifo_readers_test.v
-Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177273499 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_10 = ./usb_fifo_reader_test.v
-Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177272433 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2 
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_3 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177273481 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6 
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_4 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177369489 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_5 = ./chan_fifo_readers_test.v
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177273499 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_6 = ./usb_packet_fifo_test.v
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177365360 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0 
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_7 = ./tx_buffer_test.v
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177348942 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3 
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_8 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
+Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177366318 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 7 
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_9 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
+Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177365862 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 5 
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_10 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1175362687 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_11 = ./usb_fifo_reader_test.v
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177272433 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2 
dont_compile 0 cover_expr 0 cover_stmt 0
 Project_Sim_Count = 0
 Project_Folder_Count = 0
 Echo_Compile_Output = 0
@@ -295,6 +297,6 @@
 XML_CustomDoubleClick = 
 LOGFILE_DoubleClick = Edit
 LOGFILE_CustomDoubleClick = 
-EditorState = {tabbed horizontal 1} {Z:/wc/simulations/tx_buffer_test.v 0 1} 
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 0} 
{Z:/wc/simulations/strobe_gen_test.v 0 0} 
{Z:/wc/inband/usrp/fpga/inband_lib/chan_fifo_reader.v 0 0} 
{Z:/wc/simulations/chan_fifo_readers_test.v 0 0} 
{Z:/wc/simulations/usb_fifo_reader_test.v 0 0} 
{Z:/wc/inband/usrp/fpga/inband_lib/usb_packet_fifo.v 0 0} 
{Z:/wc/inband/usrp/fpga/inband_lib/usb_fifo_reader.v 0 0}
+EditorState = {tabbed horizontal 1} 
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 1}
 Project_Major_Version = 6
 Project_Minor_Version = 1

Modified: gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v  
2007-04-23 20:40:04 UTC (rev 5091)
+++ gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v  
2007-04-23 23:10:38 UTC (rev 5092)
@@ -1,4 +1,4 @@
-module tx_buffer_test();
+module tx_buffer_inband_test();
 
 // Inputs
 reg usbclk;
@@ -8,9 +8,6 @@
 reg WR;
 reg [3:0] channels; // ={tx_num_chan, 1b'}
 reg txclk;
-reg txstrobe;
-reg txstrobe1;
-reg txstrobe2;
 reg clear_status;
 
 // Outputs
@@ -30,6 +27,8 @@
 // Tests
 reg [15:0] i ;
 
+wire txstrobe;
+
 tx_buffer_inband tx_buffer_test (
    .usbclk(usbclk),
    .reset(reset),
@@ -51,13 +50,20 @@
    .debugbus(debug_bus)
 );
 
+strobe_gen strobe_gen_test(
+   .clock(txclk),
+   .reset(reset),
+   .enable(1'd1),
+   .rate(8'd1),
+   .strobe_in(1'd1),
+   .strobe(txstrobe) );
+    
+
 // Initialize Inputs
     initial begin
         // Setup the initial conditions
         reset = 1;
         usbclk = 0;
-        txstrobe1 = 0;
-        txstrobe2 = 0;
         usbdata = 0;
         WR = 0;
         txclk = 0;
@@ -108,25 +114,9 @@
         end
    end
 
-always @(posedge txclk) begin
-   if (txstrobe2 & txstrobe1 == 1)
-      begin
-         txstrobe1 <= 0;
-         txstrobe <= 1;
-      end
-    else if (txstrobe2 == 1)
-       txstrobe1 <= 1;
-    else
-       txstrobe <= 0;    
-end
-
 always
       #3 txclk = ~txclk ;
-      
 always
-      #12 txstrobe2 = ~txstrobe2 ;
-    
-always
       #5 usbclk = ~usbclk ; 
 
 endmodule

Modified: 
gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo_test.v    
2007-04-23 20:40:04 UTC (rev 5091)
+++ gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo_test.v    
2007-04-23 23:10:38 UTC (rev 5092)
@@ -15,6 +15,7 @@
     // Outputs
     wire [15:0] ram_data_out;
     wire is_packet;
+    wire have_space;
 
     // Instantiate the UUT
     usb_packet_fifo uut (
@@ -26,7 +27,8 @@
         .ram_data_out(ram_data_out),
         .pkt_waiting(is_packet), 
         .read_enable(read_enable), 
-        .skip_packet(skip_packet)
+        .skip_packet(skip_packet),
+        .have_space(have_space)
     );
 
 
@@ -53,7 +55,7 @@
         
         // Write an entire packets worth of data
         // into the FIFO
-        repeat (512) begin
+        repeat (256) begin
           @(posedge clock_in)
             write_enable = 1'b1 ;
             ram_data_in = i ;
@@ -75,9 +77,94 @@
           skip_packet = 1'b1 ;
         @(posedge clock_out)
           skip_packet = 1'b0 ;
+          
+          
+        i = 0;
+        repeat (256) begin
+          @(posedge clock_in)
+            write_enable = 1'b1 ;
+            ram_data_in = i ;
+          i = i + 1 ;
+        end
+        repeat (256) begin
+          @(posedge clock_in)
+            write_enable = 1'b1 ;
+            ram_data_in = i ;
+          i = i + 1 ;
+        end
+        repeat (256) begin
+          @(posedge clock_in)
+            write_enable = 1'b1 ;
+            ram_data_in = i ;
+          i = i + 1 ;
+        end
+        repeat (256) begin
+          @(posedge clock_in)
+            write_enable = 1'b1 ;
+            ram_data_in = i ;
+          i = i + 1 ;
+        end
+        @(posedge clock_in) 
+          write_enable = 1'b0 ;
+        
+        // Only read the first 10 bytes of data
+        repeat (10) begin
+          @(posedge clock_out)
+            read_enable = 1'b1 ;
+        end
+        @(posedge clock_out)
+          read_enable = 1'b0 ;
 
-    end
+        // Skip the rest of the packet
+        @(posedge clock_out)
+          skip_packet = 1'b1 ;
+        @(posedge clock_out)
+          skip_packet = 1'b0 ;
+          
+        // Only read the first 10 bytes of data
+        repeat (10) begin
+          @(posedge clock_out)
+            read_enable = 1'b1 ;
+        end
+        @(posedge clock_out)
+          read_enable = 1'b0 ;
 
+        // Skip the rest of the packet
+        @(posedge clock_out)
+          skip_packet = 1'b1 ;
+        @(posedge clock_out)
+          skip_packet = 1'b0 ;
+        
+        // Only read the first 10 bytes of data
+        repeat (10) begin
+          @(posedge clock_out)
+            read_enable = 1'b1 ;
+        end
+        @(posedge clock_out)
+          read_enable = 1'b0 ;
+
+        // Skip the rest of the packet
+        @(posedge clock_out)
+          skip_packet = 1'b1 ;
+        @(posedge clock_out)
+          skip_packet = 1'b0 ;
+          
+        // Only read the first 10 bytes of data
+        repeat (10) begin
+          @(posedge clock_out)
+            read_enable = 1'b1 ;
+        end
+        @(posedge clock_out)
+          read_enable = 1'b0 ;
+
+        // Skip the rest of the packet
+        @(posedge clock_out)
+          skip_packet = 1'b1 ;
+        @(posedge clock_out)
+          skip_packet = 1'b0 ;
+          
+       end
+
     always
       #5 clock_in = ~clock_in ;