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[Commit-gnuradio] r5108 - in gnuradio/branches/developers/matt/u2f/openc
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From: |
matt |
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Subject: |
[Commit-gnuradio] r5108 - in gnuradio/branches/developers/matt/u2f/opencores/aemb: rtl/verilog rtl/verilog/CVS sim/verilog sim/verilog/CVS sw sw/CVS sw/c sw/c/CVS |
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Date: |
Wed, 25 Apr 2007 13:52:59 -0600 (MDT) |
Author: matt
Date: 2007-04-25 13:52:59 -0600 (Wed, 25 Apr 2007)
New Revision: 5108
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/testbench.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/gccrom
Log:
updated from latest opencores, now does byte and word transfers properly
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
2007-04-25 18:21:27 UTC (rev 5107)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
2007-04-25 19:52:59 UTC (rev 5108)
@@ -1,9 +1,9 @@
-/aeMB_aslu.v/1.4/Wed Apr 11 06:30:44 2007//
/aeMB_control.v/1.3/Wed Apr 11 06:30:44 2007//
-/aeMB_core.v/1.3/Wed Apr 11 06:30:44 2007//
-/aeMB_decode.v/1.4/Wed Apr 11 06:30:44 2007//
/aeMB_fetch.v/1.3/Wed Apr 11 06:30:44 2007//
-/aeMB_regfile.v/1.8/Sat Apr 14 06:52:57 2007//
/aeMB_ucore.v/1.1/Fri Apr 13 13:02:34 2007//
/aeMB_wbbus.v/1.1/Fri Apr 13 13:02:34 2007//
+/aeMB_aslu.v/1.5/Wed Apr 25 19:45:17 2007//
+/aeMB_core.v/1.4/Wed Apr 25 19:45:17 2007//
+/aeMB_decode.v/1.5/Wed Apr 25 19:45:17 2007//
+/aeMB_regfile.v/1.9/Wed Apr 25 19:45:17 2007//
D
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
2007-04-25 18:21:27 UTC (rev 5107)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
2007-04-25 19:52:59 UTC (rev 5108)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_aslu.v,v 1.4 2007/04/11 04:30:43 sybreon Exp $
+ * $Id: aeMB_aslu.v,v 1.5 2007/04/25 22:15:04 sybreon Exp $
*
* AEMB Arithmetic Shift Logic Unit
* Copyright (C) 2006 Shawn Tan Ser Ngiap <address@hidden>
@@ -23,6 +23,9 @@
*
* HISTORY
* $Log: aeMB_aslu.v,v $
+ * Revision 1.5 2007/04/25 22:15:04 sybreon
+ * Added support for 8-bit and 16-bit data types.
+ *
* Revision 1.4 2007/04/11 04:30:43 sybreon
* Added pipeline stalling from incomplete bus cycles.
* Separated sync and async portions of code.
@@ -41,17 +44,20 @@
// address@hidden
module aeMB_aslu (/*AUTOARG*/
// Outputs
- dwb_adr_o, rRESULT,
+ dwb_adr_o, dwb_sel_o, rRESULT, rDWBSEL,
// Inputs
- dwb_dat_i, rBRA, rDLY, rREGA, rREGB, rSIMM, rMXSRC, rMXTGT, rMXALU,
+ sDWBDAT, rBRA, rDLY, rREGA, rREGB, rSIMM, rMXSRC, rMXTGT, rMXALU,
rOPC, rPC, rIMM, rRD, rRA, rMXLDST, nclk, nrst, drun, nrun
);
parameter DSIZ = 32;
output [DSIZ-1:0] dwb_adr_o;
- input [31:0] dwb_dat_i;
+ output [3:0] dwb_sel_o;
+ //input [31:0] dwb_dat_i;
output [31:0] rRESULT;
+ output [3:0] rDWBSEL;
+ input [31:0] sDWBDAT;
input rBRA, rDLY;
input [31:0] rREGA, rREGB;
input [31:0] rSIMM;
@@ -67,18 +73,54 @@
reg [31:0] rRESULT, xRESULT;
reg rMSR_C, xMSR_C;
+
+ // Operands
+ wire [31:0] wOPA, wOPB;
+ // DWB I/F
+ reg [31:0] rDWBADR;
+ wire [31:0] wDWBADR;
+
+ assign dwb_adr_o = {rDWBADR[DSIZ-1:2],2'b00};
+ assign wDWBADR = (wOPA + wOPB);
+
+ reg [3:0] rDWBSEL, xDWBSEL;
+
+ always @(/*AUTOSENSE*/rOPC or wDWBADR)
+ case (wDWBADR[1:0])
+ 2'o0: case (rOPC[1:0])
+ 2'o0: xDWBSEL <= 4'h8;
+ 2'o1: xDWBSEL <= 4'hC;
+ default: xDWBSEL <= 4'hF;
+ endcase // case (rOPC[1:0])
+ 2'o1: case (rOPC[1:0])
+ 2'o0: xDWBSEL <= 4'h4;
+ default: xDWBSEL <= 4'h0;
+ endcase // case (rOPC[1:0])
+ 2'o2: case (rOPC[1:0])
+ 2'o0: xDWBSEL <= 4'h2;
+ 2'o1: xDWBSEL <= 4'h3;
+ default: xDWBSEL <= 4'h0;
+ endcase // case (rOPC[1:0])
+ 2'o3: case (rOPC[1:0])
+ 2'o0: xDWBSEL <= 4'h1;
+ default: xDWBSEL <= 4'h0;
+ endcase // case (rOPC[1:0])
+ endcase // case (wDWBADR[1:0])
+
+
// Endian correction
- //wire [31:0] wDWBDAT = dwb_dat_i;
- wire [31:0] wDWBDAT =
{dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]};
+ wire [31:0] wDWBDAT;
+ assign dwb_sel_o = {rDWBSEL[0],rDWBSEL[1],rDWBSEL[2],rDWBSEL[3]};
+ assign wDWBDAT = sDWBDAT;
// Source and Target Select
- wire [31:0] wOPA =
+ assign wOPA =
(rMXSRC == 2'b11) ? wDWBDAT :
(rMXSRC == 2'b10) ? rRESULT :
(rMXSRC == 2'b01) ? rPC :
rREGA;
- wire [31:0] wOPB =
+ assign wOPB =
(rMXTGT == 2'b11) ? wDWBDAT :
(rMXTGT == 2'b10) ? rRESULT :
(rMXTGT == 2'b01) ? rSIMM :
@@ -151,10 +193,6 @@
always @(/*AUTOSENSE*/rRA or wOPA or wOPB)
rRES_M <= #1 (rRA[3]) ? wOPB : wOPA;
- // DWB I/F
- //assign dwb_adr_o = rRESULT;
- assign dwb_adr_o = {rRESULT[DSIZ-1:2],2'b00};
-
// RESULT + C
always @(/*AUTOSENSE*/drun or rMSR_C or rMXALU or rOPC or rRES_A
or rRES_AC or rRES_L or rRES_M or rRES_S or rRES_SC)
@@ -183,12 +221,16 @@
if (!nrst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
+ rDWBADR <= 32'h0;
+ rDWBSEL <= 4'h0;
rMSR_C <= 1'h0;
rRESULT <= 32'h0;
// End of automatics
end else if (nrun) begin
rRESULT <= #1 xRESULT;
- rMSR_C <= #1 xMSR_C;
+ rMSR_C <= #1 xMSR_C;
+ rDWBADR <= #1 wDWBADR;
+ rDWBSEL <= #1 xDWBSEL;
end
endmodule // aeMB_aslu
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
2007-04-25 18:21:27 UTC (rev 5107)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
2007-04-25 19:52:59 UTC (rev 5108)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_core.v,v 1.3 2007/04/11 04:30:43 sybreon Exp $
+ * $Id: aeMB_core.v,v 1.4 2007/04/25 22:15:04 sybreon Exp $
*
* AEMB 32-bit Microblaze Compatible Core
* Copyright (C) 2006 Shawn Tan Ser Ngiap <address@hidden>
@@ -25,6 +25,9 @@
*
* HISTORY
* $Log: aeMB_core.v,v $
+ * Revision 1.4 2007/04/25 22:15:04 sybreon
+ * Added support for 8-bit and 16-bit data types.
+ *
* Revision 1.3 2007/04/11 04:30:43 sybreon
* Added pipeline stalling from incomplete bus cycles.
* Separated sync and async portions of code.
@@ -39,7 +42,8 @@
module aeMB_core (/*AUTOARG*/
// Outputs
- iwb_stb_o, iwb_adr_o, dwb_we_o, dwb_stb_o, dwb_dat_o, dwb_adr_o,
+ iwb_stb_o, iwb_adr_o, dwb_we_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
+ dwb_adr_o,
// Inputs
sys_rst_i, sys_int_i, sys_exc_i, sys_clk_i, iwb_dat_i, iwb_ack_i,
dwb_dat_i, dwb_ack_i
@@ -53,6 +57,7 @@
// Beginning of automatic outputs (from unused autoinst outputs)
output [DSIZ-1:0] dwb_adr_o; // From aslu of aeMB_aslu.v
output [31:0] dwb_dat_o; // From regfile of
aeMB_regfile.v
+ output [3:0] dwb_sel_o; // From aslu of
aeMB_aslu.v
output dwb_stb_o; // From decode of aeMB_decode.v
output dwb_we_o; // From decode of aeMB_decode.v
output [ISIZ-1:0] iwb_adr_o; // From fetch of aeMB_fetch.v
@@ -61,7 +66,7 @@
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input dwb_ack_i; // To control of aeMB_control.v
- input [31:0] dwb_dat_i; // To regfile of
aeMB_regfile.v, ...
+ input [31:0] dwb_dat_i; // To regfile of
aeMB_regfile.v
input iwb_ack_i; // To control of aeMB_control.v
input [31:0] iwb_dat_i; // To fetch of
aeMB_fetch.v, ...
input sys_clk_i; // To control of aeMB_control.v
@@ -78,6 +83,7 @@
wire nrun; // From control of
aeMB_control.v
wire rBRA; // From decode of
aeMB_decode.v
wire rDLY; // From decode of
aeMB_decode.v
+ wire [3:0] rDWBSEL; // From aslu of aeMB_aslu.v
wire rDWBSTB; // From decode of
aeMB_decode.v
wire rDWBWE; // From decode of
aeMB_decode.v
wire [1:0] rFSM; // From control of
aeMB_control.v
@@ -99,6 +105,7 @@
wire [31:0] rRESULT; // From aslu of aeMB_aslu.v
wire rRWE; // From decode of
aeMB_decode.v
wire [31:0] rSIMM; // From decode of aeMB_decode.v
+ wire [31:0] sDWBDAT; // From regfile of
aeMB_regfile.v
// End of automatics
aeMB_regfile #(DSIZ)
@@ -107,6 +114,7 @@
.dwb_dat_o (dwb_dat_o[31:0]),
.rREGA (rREGA[31:0]),
.rREGB (rREGB[31:0]),
+ .sDWBDAT (sDWBDAT[31:0]),
// Inputs
.dwb_dat_i (dwb_dat_i[31:0]),
.rDWBSTB (rDWBSTB),
@@ -118,6 +126,8 @@
.rRESULT (rRESULT[31:0]),
.rFSM (rFSM[1:0]),
.rPC (rPC[31:0]),
+ .rOPC (rOPC[5:0]),
+ .rDWBSEL (rDWBSEL[3:0]),
.rLNK (rLNK),
.rRWE (rRWE),
.nclk (nclk),
@@ -164,9 +174,11 @@
aslu (/*AUTOINST*/
// Outputs
.dwb_adr_o (dwb_adr_o[DSIZ-1:0]),
+ .dwb_sel_o (dwb_sel_o[3:0]),
.rRESULT (rRESULT[31:0]),
+ .rDWBSEL (rDWBSEL[3:0]),
// Inputs
- .dwb_dat_i (dwb_dat_i[31:0]),
+ .sDWBDAT (sDWBDAT[31:0]),
.rBRA (rBRA),
.rDLY (rDLY),
.rREGA (rREGA[31:0]),
@@ -211,10 +223,11 @@
.dwb_stb_o (dwb_stb_o),
.dwb_we_o (dwb_we_o),
// Inputs
+ .sDWBDAT (sDWBDAT[31:0]),
+ .rDWBSEL (rDWBSEL[3:0]),
.rREGA (rREGA[31:0]),
.rRESULT (rRESULT[31:0]),
.iwb_dat_i (iwb_dat_i[31:0]),
- .dwb_dat_i (dwb_dat_i[31:0]),
.nclk (nclk),
.nrst (nrst),
.drun (drun),
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
2007-04-25 18:21:27 UTC (rev 5107)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
2007-04-25 19:52:59 UTC (rev 5108)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_decode.v,v 1.4 2007/04/11 04:30:43 sybreon Exp $
+ * $Id: aeMB_decode.v,v 1.5 2007/04/25 22:15:04 sybreon Exp $
*
* AEMB Instruction Decoder
* Copyright (C) 2006 Shawn Tan Ser Ngiap <address@hidden>
@@ -23,6 +23,9 @@
*
* HISTORY
* $Log: aeMB_decode.v,v $
+ * Revision 1.5 2007/04/25 22:15:04 sybreon
+ * Added support for 8-bit and 16-bit data types.
+ *
* Revision 1.4 2007/04/11 04:30:43 sybreon
* Added pipeline stalling from incomplete bus cycles.
* Separated sync and async portions of code.
@@ -45,7 +48,8 @@
rDWBSTB, rDWBWE, rIWBSTB, rDLY, rLNK, rBRA, rRWE, rMXLDST,
iwb_stb_o, dwb_stb_o, dwb_we_o,
// Inputs
- rREGA, rRESULT, iwb_dat_i, dwb_dat_i, nclk, nrst, drun, frun, nrun
+ sDWBDAT, rDWBSEL, rREGA, rRESULT, iwb_dat_i, nclk, nrst, drun,
+ frun, nrun
);
// Internal I/F
output [31:0] rSIMM;
@@ -56,11 +60,14 @@
output [15:0] rIMM;
output rDWBSTB, rDWBWE, rIWBSTB;
output rDLY, rLNK, rBRA, rRWE;
- output [1:0] rMXLDST;
+ output [1:0] rMXLDST;
+ input [31:0] sDWBDAT;
+ input [3:0] rDWBSEL;
input [31:0] rREGA, rRESULT;
// External I/F
- input [31:0] iwb_dat_i, dwb_dat_i;
+ input [31:0] iwb_dat_i;
+ //, dwb_dat_i;
output iwb_stb_o;
output dwb_stb_o, dwb_we_o;
@@ -68,11 +75,11 @@
input nclk, nrst, drun, frun, nrun;
// Endian Correction
- //wire [31:0] wWBDAT = dwb_dat_i;
- //wire [31:0] wIREG = iwb_dat_i;
- wire [31:0] wWBDAT =
{dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]};
- wire [31:0] wIREG =
{iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]};
-
+ wire [31:0] wIREG;
+ wire [31:0] wWBDAT;
+ assign wIREG =
{iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]};
+ assign wWBDAT = sDWBDAT;
+
// Decode
wire [5:0] wOPC = wIREG[31:26];
wire [4:0] wRD = wIREG[25:21];
@@ -398,7 +405,7 @@
rSIMM <= #1 xSIMM;
rFIMM <= #1 xFIMM;
rIMMHI <= #1 xIMMHI;
- end // else: !if(!nrst)
+ end // if (nrun)
always @(negedge nclk or negedge nrst)
if (!nrst) begin
@@ -420,7 +427,7 @@
rRWE <= #1 xRWE;
rDWBSTB <= #1 xDWBSTB;
rDWBWE <= #1 xDWBWE;
- end // else: !if(!nrst)
+ end
endmodule // aeMB_decode
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
2007-04-25 18:21:27 UTC (rev 5107)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
2007-04-25 19:52:59 UTC (rev 5108)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_regfile.v,v 1.8 2007/04/12 20:21:33 sybreon Exp $
+ * $Id: aeMB_regfile.v,v 1.9 2007/04/25 22:15:04 sybreon Exp $
*
* AEMB Register File
* Copyright (C) 2006 Shawn Tan Ser Ngiap <address@hidden>
@@ -25,6 +25,9 @@
*
* HISTORY
* $Log: aeMB_regfile.v,v $
+ * Revision 1.9 2007/04/25 22:15:04 sybreon
+ * Added support for 8-bit and 16-bit data types.
+ *
* Revision 1.8 2007/04/12 20:21:33 sybreon
* Moved testbench into /sim/verilog.
* Simulation cleanups.
@@ -57,10 +60,10 @@
// address@hidden - RAM
module aeMB_regfile(/*AUTOARG*/
// Outputs
- dwb_dat_o, rREGA, rREGB,
+ dwb_dat_o, rREGA, rREGB, sDWBDAT,
// Inputs
dwb_dat_i, rDWBSTB, rDWBWE, rRA, rRB, rRD, rRD_, rRESULT, rFSM,
- rPC, rLNK, rRWE, nclk, nrst, drun, nrun
+ rPC, rOPC, rDWBSEL, rLNK, rRWE, nclk, nrst, drun, nrun
);
// Data WB bus width
parameter DSIZ = 32;
@@ -71,11 +74,15 @@
// Internal I/F
output [31:0] rREGA, rREGB;
+ output [31:0] sDWBDAT;
+
input rDWBSTB, rDWBWE;
input [4:0] rRA, rRB, rRD, rRD_;
input [31:0] rRESULT;
input [1:0] rFSM;
input [31:0] rPC;
+ input [5:0] rOPC;
+ input [3:0] rDWBSEL;
//, rPCNXT;
input rLNK, rRWE;
input nclk, nrst, drun, nrun;
@@ -104,277 +111,34 @@
end
// DWB data - Endian Correction
- reg [31:0] rDWBDAT, xDWBDAT;
- //assign dwb_dat_o = rDWBDAT;
- //wire [31:0] wDWBDAT = dwb_dat_i;
+ wire [31:0] wDWBDAT;
+ reg [31:0] sDWBDAT;
+ reg [31:0] rDWBDAT;
assign dwb_dat_o =
{rDWBDAT[7:0],rDWBDAT[15:8],rDWBDAT[23:16],rDWBDAT[31:24]};
- wire [31:0] wDWBDAT =
{dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]};
+ assign wDWBDAT =
{dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]};
+ always @(/*AUTOSENSE*/rDWBSEL or wDWBDAT)
+ case (rDWBSEL)
+ 4'hF: sDWBDAT <= wDWBDAT;
+ 4'hC: sDWBDAT <= {(16){1'b0},wDWBDAT[31:16]};
+ 4'h3: sDWBDAT <= {(16){1'b0},wDWBDAT[15:0]};
+ 4'h8: sDWBDAT <= {(24){1'b0},wDWBDAT[31:24]};
+ 4'h4: sDWBDAT <= {(24){1'b0},wDWBDAT[23:16]};
+ 4'h2: sDWBDAT <= {(24){1'b0},wDWBDAT[15:8]};
+ 4'h1: sDWBDAT <= {(24){1'b0},wDWBDAT[7:0]};
+ default: sDWBDAT <= 32'h0;
+ endcase // case (rDWBSEL)
+
// Forwarding Control
wire fDFWD = (rRD == rRD_) & fWE;
wire fMFWD = rDWBSTB & ~rDWBWE;
- wire [31:0] wRESULT = (fMFWD) ? wDWBDAT : rRESULT;
-
- // Register Load
- always @(/*AUTOSENSE*/drun or fDFWD or r00 or r01 or r02 or r03
- or r04 or r05 or r06 or r07 or r08 or r09 or r0A or r0B
- or r0C or r0D or r0E or r0F or r10 or r11 or r12 or r13
- or r14 or r15 or r16 or r17 or r18 or r19 or r1A or r1B
- or r1C or r1D or r1E or r1F or rRD or wRESULT)
- if (drun) begin
- case (rRD)
- 5'h00: xDWBDAT <= (fDFWD) ? wRESULT : r00;
- 5'h01: xDWBDAT <= (fDFWD) ? wRESULT : r01;
- 5'h02: xDWBDAT <= (fDFWD) ? wRESULT : r02;
- 5'h03: xDWBDAT <= (fDFWD) ? wRESULT : r03;
- 5'h04: xDWBDAT <= (fDFWD) ? wRESULT : r04;
- 5'h05: xDWBDAT <= (fDFWD) ? wRESULT : r05;
- 5'h06: xDWBDAT <= (fDFWD) ? wRESULT : r06;
- 5'h07: xDWBDAT <= (fDFWD) ? wRESULT : r07;
- 5'h08: xDWBDAT <= (fDFWD) ? wRESULT : r08;
- 5'h09: xDWBDAT <= (fDFWD) ? wRESULT : r09;
- 5'h0A: xDWBDAT <= (fDFWD) ? wRESULT : r0A;
- 5'h0B: xDWBDAT <= (fDFWD) ? wRESULT : r0B;
- 5'h0C: xDWBDAT <= (fDFWD) ? wRESULT : r0C;
- 5'h0D: xDWBDAT <= (fDFWD) ? wRESULT : r0D;
- 5'h0E: xDWBDAT <= (fDFWD) ? wRESULT : r0E;
- 5'h0F: xDWBDAT <= (fDFWD) ? wRESULT : r0F;
- 5'h10: xDWBDAT <= (fDFWD) ? wRESULT : r10;
- 5'h11: xDWBDAT <= (fDFWD) ? wRESULT : r11;
- 5'h12: xDWBDAT <= (fDFWD) ? wRESULT : r12;
- 5'h13: xDWBDAT <= (fDFWD) ? wRESULT : r13;
- 5'h14: xDWBDAT <= (fDFWD) ? wRESULT : r14;
- 5'h15: xDWBDAT <= (fDFWD) ? wRESULT : r15;
- 5'h16: xDWBDAT <= (fDFWD) ? wRESULT : r16;
- 5'h17: xDWBDAT <= (fDFWD) ? wRESULT : r17;
- 5'h18: xDWBDAT <= (fDFWD) ? wRESULT : r18;
- 5'h19: xDWBDAT <= (fDFWD) ? wRESULT : r19;
- 5'h1A: xDWBDAT <= (fDFWD) ? wRESULT : r1A;
- 5'h1B: xDWBDAT <= (fDFWD) ? wRESULT : r1B;
- 5'h1C: xDWBDAT <= (fDFWD) ? wRESULT : r1C;
- 5'h1D: xDWBDAT <= (fDFWD) ? wRESULT : r1D;
- 5'h1E: xDWBDAT <= (fDFWD) ? wRESULT : r1E;
- 5'h1F: xDWBDAT <= (fDFWD) ? wRESULT : r1F;
- endcase // case (rRD)
- end else begin // if (drun)
- /*AUTORESET*/
- // Beginning of autoreset for uninitialized flops
- xDWBDAT <= 32'h0;
- // End of automatics
- end // else: !if(drun)
-
- // Load Registers
- reg [31:0] xREGA, xREGB;
- always @(/*AUTOSENSE*/drun or r00 or r01 or r02 or r03 or r04
- or r05 or r06 or r07 or r08 or r09 or r0A or r0B or r0C
- or r0D or r0E or r0F or r10 or r11 or r12 or r13 or r14
- or r15 or r16 or r17 or r18 or r19 or r1A or r1B or r1C
- or r1D or r1E or r1F or rRA or rRB)
- if (drun) begin
- case (rRA)
- 5'h1F: xREGA <= r1F;
- 5'h1E: xREGA <= r1E;
- 5'h1D: xREGA <= r1D;
- 5'h1C: xREGA <= r1C;
- 5'h1B: xREGA <= r1B;
- 5'h1A: xREGA <= r1A;
- 5'h19: xREGA <= r19;
- 5'h18: xREGA <= r18;
- 5'h17: xREGA <= r17;
- 5'h16: xREGA <= r16;
- 5'h15: xREGA <= r15;
- 5'h14: xREGA <= r14;
- 5'h13: xREGA <= r13;
- 5'h12: xREGA <= r12;
- 5'h11: xREGA <= r11;
- 5'h10: xREGA <= r10;
- 5'h0F: xREGA <= r0F;
- 5'h0E: xREGA <= r0E;
- 5'h0D: xREGA <= r0D;
- 5'h0C: xREGA <= r0C;
- 5'h0B: xREGA <= r0B;
- 5'h0A: xREGA <= r0A;
- 5'h09: xREGA <= r09;
- 5'h08: xREGA <= r08;
- 5'h07: xREGA <= r07;
- 5'h06: xREGA <= r06;
- 5'h05: xREGA <= r05;
- 5'h04: xREGA <= r04;
- 5'h03: xREGA <= r03;
- 5'h02: xREGA <= r02;
- 5'h01: xREGA <= r01;
- 5'h00: xREGA <= r00;
- endcase // case (rRA)
-
- case (rRB)
- 5'h1F: xREGB <= r1F;
- 5'h1E: xREGB <= r1E;
- 5'h1D: xREGB <= r1D;
- 5'h1C: xREGB <= r1C;
- 5'h1B: xREGB <= r1B;
- 5'h1A: xREGB <= r1A;
- 5'h19: xREGB <= r19;
- 5'h18: xREGB <= r18;
- 5'h17: xREGB <= r17;
- 5'h16: xREGB <= r16;
- 5'h15: xREGB <= r15;
- 5'h14: xREGB <= r14;
- 5'h13: xREGB <= r13;
- 5'h12: xREGB <= r12;
- 5'h11: xREGB <= r11;
- 5'h10: xREGB <= r10;
- 5'h0F: xREGB <= r0F;
- 5'h0E: xREGB <= r0E;
- 5'h0D: xREGB <= r0D;
- 5'h0C: xREGB <= r0C;
- 5'h0B: xREGB <= r0B;
- 5'h0A: xREGB <= r0A;
- 5'h09: xREGB <= r09;
- 5'h08: xREGB <= r08;
- 5'h07: xREGB <= r07;
- 5'h06: xREGB <= r06;
- 5'h05: xREGB <= r05;
- 5'h04: xREGB <= r04;
- 5'h03: xREGB <= r03;
- 5'h02: xREGB <= r02;
- 5'h01: xREGB <= r01;
- 5'h00: xREGB <= r00;
- endcase // case (rRB)
- end else begin // if (drun)
- /*AUTORESET*/
- // Beginning of autoreset for uninitialized flops
- xREGA <= 32'h0;
- xREGB <= 32'h0;
- // End of automatics
- end // else: !if(drun)
-
-
- // Normal Registers
- wire fR00 = (rRD_ == 5'h00);
- wire fR01 = (rRD_ == 5'h01);
- wire fR02 = (rRD_ == 5'h02);
- wire fR03 = (rRD_ == 5'h03);
- wire fR04 = (rRD_ == 5'h04);
- wire fR05 = (rRD_ == 5'h05);
- wire fR06 = (rRD_ == 5'h06);
- wire fR07 = (rRD_ == 5'h07);
- wire fR08 = (rRD_ == 5'h08);
- wire fR09 = (rRD_ == 5'h09);
- wire fR0A = (rRD_ == 5'h0A);
- wire fR0B = (rRD_ == 5'h0B);
- wire fR0C = (rRD_ == 5'h0C);
- wire fR0D = (rRD_ == 5'h0D);
- wire fR0E = (rRD_ == 5'h0E);
- wire fR0F = (rRD_ == 5'h0F);
- wire fR10 = (rRD_ == 5'h10);
- wire fR11 = (rRD_ == 5'h11);
- wire fR12 = (rRD_ == 5'h12);
- wire fR13 = (rRD_ == 5'h13);
- wire fR14 = (rRD_ == 5'h14);
- wire fR15 = (rRD_ == 5'h15);
- wire fR16 = (rRD_ == 5'h16);
- wire fR17 = (rRD_ == 5'h17);
- wire fR18 = (rRD_ == 5'h18);
- wire fR19 = (rRD_ == 5'h19);
- wire fR1A = (rRD_ == 5'h1A);
- wire fR1B = (rRD_ == 5'h1B);
- wire fR1C = (rRD_ == 5'h1C);
- wire fR1D = (rRD_ == 5'h1D);
- wire fR1E = (rRD_ == 5'h1E);
- wire fR1F = (rRD_ == 5'h1F);
-
- always @(negedge nclk or negedge nrst)
- if (!nrst) begin
- /*AUTORESET*/
- // Beginning of autoreset for uninitialized flops
- r01 <= 32'h0;
- r02 <= 32'h0;
- r03 <= 32'h0;
- r04 <= 32'h0;
- r05 <= 32'h0;
- r06 <= 32'h0;
- r07 <= 32'h0;
- r08 <= 32'h0;
- r09 <= 32'h0;
- r0A <= 32'h0;
- r0B <= 32'h0;
- r0C <= 32'h0;
- r0D <= 32'h0;
- r0F <= 32'h0;
- r10 <= 32'h0;
- r12 <= 32'h0;
- r13 <= 32'h0;
- r14 <= 32'h0;
- r15 <= 32'h0;
- r16 <= 32'h0;
- r17 <= 32'h0;
- r18 <= 32'h0;
- r19 <= 32'h0;
- r1A <= 32'h0;
- r1B <= 32'h0;
- r1C <= 32'h0;
- r1D <= 32'h0;
- r1E <= 32'h0;
- r1F <= 32'h0;
- // End of automatics
- end else begin // if (!nrst)
- r01 <= #1 (!fR01) ? r01 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r01;
- r02 <= #1 (!fR02) ? r02 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r02;
- r03 <= #1 (!fR03) ? r03 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r03;
- r04 <= #1 (!fR04) ? r04 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r04;
- r05 <= #1 (!fR05) ? r05 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r05;
- r06 <= #1 (!fR06) ? r06 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r06;
- r07 <= #1 (!fR07) ? r07 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r07;
- r08 <= #1 (!fR08) ? r08 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r08;
- r09 <= #1 (!fR09) ? r09 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r09;
- r0A <= #1 (!fR0A) ? r0A : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r0A;
- r0B <= #1 (!fR0B) ? r0B : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r0B;
- r0C <= #1 (!fR0C) ? r0C : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r0C;
- r0D <= #1 (!fR0D) ? r0D : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r0D;
- r0F <= #1 (!fR0F) ? r0F : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r0F;
- r10 <= #1 (!fR10) ? r10 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r10;
- r12 <= #1 (!fR12) ? r12 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r12;
- r13 <= #1 (!fR13) ? r13 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r13;
- r14 <= #1 (!fR14) ? r14 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r14;
- r15 <= #1 (!fR15) ? r15 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r15;
- r16 <= #1 (!fR16) ? r16 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r16;
- r17 <= #1 (!fR17) ? r17 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r17;
- r18 <= #1 (!fR18) ? r18 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r18;
- r19 <= #1 (!fR19) ? r19 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r19;
- r1A <= #1 (!fR1A) ? r1A : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r1A;
- r1B <= #1 (!fR1B) ? r1B : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r1B;
- r1C <= #1 (!fR1C) ? r1C : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r1C;
- r1D <= #1 (!fR1D) ? r1D : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r1D;
- r1E <= #1 (!fR1E) ? r1E : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r1E;
- r1F <= #1 (!fR1F) ? r1F : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r1F;
-
- end // else: !if(!nrst)
-
- // Special Registers
- always @(negedge nclk or negedge nrst)
- if (!nrst) begin
- /*AUTORESET*/
- // Beginning of autoreset for uninitialized flops
- r00 <= 32'h0;
- r0E <= 32'h0;
- r11 <= 32'h0;
- // End of automatics
- end else begin
- // R00 - Zero
- r00 <= #1 r00;
- // R0E - Interrupt
- r0E <= #1 //(rFSM == 2'b01) ? rPCNXT :
- (!fR0E) ? r0E : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r0E;
- // R11 - Exception
- r11 <= #1 //(rFSM == 2'b10) ? rPCNXT :
- (!fR11) ? r11 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r11;
- end // else: !if(!nrst)
-
+ wire [31:0] wRESULT = (fMFWD) ? sDWBDAT : rRESULT;
+
// Alternative Design
reg [31:0] rMEMA[0:31], rMEMB[0:31], rMEMD[0:31];
wire [31:0] wDDAT, wREGA, wREGB, wREGD, wWBDAT;
wire wDWE = (fLD | fLNK | fWE) & |rRD_ & nrun;
- assign wDDAT = (fLD) ? wDWBDAT :
+ assign wDDAT = (fLD) ? sDWBDAT :
(fLNK) ? rPC_ : rRESULT;
assign wWBDAT = (fDFWD) ? wRESULT : wREGD;
@@ -388,14 +152,21 @@
rMEMB[rRD_] <= wDDAT;
rMEMD[rRD_] <= wDDAT;
end
+
+ // Resize
+ reg [31:0] sWBDAT;
+ always @(/*AUTOSENSE*/rOPC or wWBDAT)
+ case (rOPC[1:0])
+ 2'o0: sWBDAT <= {(4){wWBDAT[7:0]}};
+ 2'o1: sWBDAT <= {(2){wWBDAT[15:0]}};
+ default: sWBDAT <= wWBDAT;
+ endcase // case (rOPC[1:0])
// PIPELINE REGISTERS //////////////////////////////////////////////////
reg [31:0] rREGA, rREGB;
always @(/*AUTOSENSE*/wREGA or wREGB)
begin
- //rREGA <= #1 xREGA;
- //rREGB <= #1 xREGB;
rREGA <= #1 wREGA;
rREGB <= #1 wREGB;
end
@@ -407,8 +178,7 @@
rDWBDAT <= 32'h0;
// End of automatics
end else if (nrun) begin
- //rDWBDAT <= #1 xDWBDAT;
- rDWBDAT <= #1 wWBDAT;
+ rDWBDAT <= #1 sWBDAT;
end
// SIMULATION ONLY ///////////////////////////////////////////////////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
2007-04-25 18:21:27 UTC (rev 5107)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
2007-04-25 19:52:59 UTC (rev 5108)
@@ -1,3 +1,3 @@
-/testbench.v/1.1/Thu Apr 12 20:21:34 2007//
/utestbench.v/1.1/Fri Apr 13 13:02:34 2007//
+/testbench.v/1.2/Wed Apr 25 19:45:17 2007//
D
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/testbench.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/testbench.v
2007-04-25 18:21:27 UTC (rev 5107)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/testbench.v
2007-04-25 19:52:59 UTC (rev 5108)
@@ -1,5 +1,5 @@
/*
- * $Id: testbench.v,v 1.1 2007/04/12 20:21:34 sybreon Exp $
+ * $Id: testbench.v,v 1.2 2007/04/25 22:15:05 sybreon Exp $
*
* AEMB Generic Testbench
* Copyright (C) 2006 Shawn Tan Ser Ngiap <address@hidden>
@@ -23,30 +23,24 @@
*
* HISTORY
* $Log: testbench.v,v $
+ * Revision 1.2 2007/04/25 22:15:05 sybreon
+ * Added support for 8-bit and 16-bit data types.
+ *
* Revision 1.1 2007/04/12 20:21:34 sybreon
* Moved testbench into /sim/verilog.
* Simulation cleanups.
*
- * Revision 1.4 2007/04/11 04:30:43 sybreon
- * Added pipeline stalling from incomplete bus cycles.
- * Separated sync and async portions of code.
- *
- * Revision 1.3 2007/04/04 14:08:34 sybreon
- * Added initial interrupt/exception support.
- *
- * Revision 1.2 2007/04/04 06:11:59 sybreon
- * Extended testbench code
- *
- * Revision 1.1 2007/03/09 17:52:17 sybreon
- * initial import
- *
*/
module testbench ();
parameter ISIZ = 16;
parameter DSIZ = 16;
+
- reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
+ // INITIAL SETUP //////////////////////////////////////////////////////
+
+ reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
+ always #5 sys_clk_i = ~sys_clk_i;
initial begin
$dumpfile("dump.vcd");
@@ -68,36 +62,46 @@
//#11000 $finish;
join
- always #5 sys_clk_i = ~sys_clk_i;
-
- // FAKE ROM
- reg [31:0] rom [0:65535];
- wire [31:0] iwb_dat_i;
- reg iwb_ack_i, dwb_ack_i;
+ // FAKE MEMORY ////////////////////////////////////////////////////////
+
wire [ISIZ-1:0] iwb_adr_o;
- wire iwb_stb_o;
- wire dwb_stb_o;
+ wire iwb_stb_o;
+ wire dwb_stb_o;
+ reg [31:0] rom [0:65535];
+ wire [31:0] iwb_dat_i;
+ reg iwb_ack_i, dwb_ack_i;
- // FAKE RAM
- reg [31:0] ram [0:65535];
- wire [31:0] dwb_dat_i;
- reg [31:0] dwblat;
- wire dwb_we_o;
- reg [DSIZ-1:2] dadr,iadr;
- wire [31:0] dwb_dat_o;
+ reg [31:0] ram[0:65535];
+ wire [31:0] dwb_dat_i;
+ reg [31:0] dwblat;
+ wire dwb_we_o;
+ reg [DSIZ-1:2] dadr,iadr;
+ wire [3:0] dwb_sel_o;
+ wire [31:0] dwb_dat_o;
wire [DSIZ-1:0] dwb_adr_o;
-
+ wire [31:0] dwb_dat_t;
+
assign dwb_dat_i = ram[dadr];
- assign iwb_dat_i = ram[iadr];
+ assign iwb_dat_i = ram[iadr];
+ assign dwb_dat_t = ram[dwb_adr_o[DSIZ-1:2]];
+
always @(posedge sys_clk_i) begin
iwb_ack_i <= #1 iwb_stb_o;
- //& $random;
dwb_ack_i <= #1 dwb_stb_o;
- //& $random;
iadr <= #1 iwb_adr_o[ISIZ-1:2];
- ram[dwb_adr_o[DSIZ-1:2]] <= (dwb_we_o & dwb_stb_o) ? dwb_dat_o :
ram[dwb_adr_o[DSIZ-1:2]];
- dwblat <= dwb_adr_o;
- dadr <= dwb_adr_o[DSIZ-1:2];
+ dadr <= dwb_adr_o[DSIZ-1:2];
+
+ if (dwb_we_o & dwb_stb_o) begin
+ case (dwb_sel_o)
+ 4'h1: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:8],dwb_dat_o[7:0]};
+ 4'h2: ram[dwb_adr_o[DSIZ-1:2]] <=
{dwb_dat_t[31:16],dwb_dat_o[15:8],dwb_dat_t[7:0]};
+ 4'h4: ram[dwb_adr_o[DSIZ-1:2]] <=
{dwb_dat_t[31:24],dwb_dat_o[23:16],dwb_dat_t[15:0]};
+ 4'h8: ram[dwb_adr_o[DSIZ-1:2]] <=
{dwb_dat_o[31:24],dwb_dat_t[23:0]};
+ 4'h3: ram[dwb_adr_o[DSIZ-1:2]] <=
{dwb_dat_t[31:16],dwb_dat_o[15:0]};
+ 4'hC: ram[dwb_adr_o[DSIZ-1:2]] <=
{dwb_dat_o[31:16],dwb_dat_t[15:0]};
+ 4'hF: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[31:0]};
+ endcase // case (dwb_sel_o)
+ end
end
integer i;
@@ -105,34 +109,49 @@
for (i=0;i<65535;i=i+1) begin
ram[i] <= 32'h0;
end
- #1 $readmemh("aeMB.rom",ram);
+ #1 $readmemh("aeMB.rom",ram);
end
+ // DISPLAY OUTPUTS ///////////////////////////////////////////////////
+
always @(negedge sys_clk_i) begin
+
$write("\nT: ",$stime);
if (iwb_stb_o & iwb_ack_i)
$writeh("\tPC: 0x",iwb_adr_o,"=0x",iwb_dat_i);
if (dwb_stb_o & dwb_we_o & dwb_ack_i)
- $writeh("\tST: 0x",dwb_adr_o,"=0x",dwb_dat_o);
+ $writeh("\tST: 0x",dwb_adr_o,"=0x",dwb_dat_o," S=0x",dwb_sel_o);
if (dwb_stb_o & ~dwb_we_o & dwb_ack_i)
- $writeh("\tLD: 0x",dwb_adr_o,"=0x",dwb_dat_i);
-
+ $writeh("\tLD: 0x",dwb_adr_o,"=0x",dwb_dat_i," S=0x",dwb_sel_o);
if (dut.regfile.wDWE)
- $writeh("\tR",dut.regfile.rRD_,"=",dut.regfile.wDDAT,";");
+ $writeh("\tR",dut.regfile.rRD_,"=",dut.regfile.wDDAT,";");
if ((dwb_adr_o == 16'h8888) && (dwb_dat_o == 32'h7a55ed00))
$display("*** SERVICE ***");
-
if (dut.control.rFSM == 2'o1)
- $display("*** INTERRUPT ***");
+ $display("*** INTERRUPT ***");
+
+ if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
+ $display("\tFAIL");
+ $finish;
+ end
+ if (dwb_we_o & (dwb_dat_o == "PASS")) begin
+ $display("\tPASS");
+ end
+ if (iwb_dat_i == 32'h000000b8) begin
+ $display("\n\t*** PASSED ALL TESTS ***");
+ $finish;
+ end
+ end // always @ (posedge sys_clk_i)
- end // always @ (posedge sys_clk_i)
+ // INTERNAL WIRING ////////////////////////////////////////////////////
aeMB_core #(ISIZ,DSIZ)
dut (
.sys_int_i(sys_int_i),.sys_exc_i(sys_exc_i),
.dwb_ack_i(dwb_ack_i),.dwb_stb_o(dwb_stb_o),.dwb_adr_o(dwb_adr_o),
.dwb_dat_o(dwb_dat_o),.dwb_dat_i(dwb_dat_i),.dwb_we_o(dwb_we_o),
+ .dwb_sel_o(dwb_sel_o),
.iwb_adr_o(iwb_adr_o),.iwb_dat_i(iwb_dat_i),.iwb_stb_o(iwb_stb_o),
.iwb_ack_i(iwb_ack_i),
.sys_clk_i(sys_clk_i), .sys_rst_i(sys_rst_i)
Modified: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
2007-04-25 18:21:27 UTC (rev 5107)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
2007-04-25 19:52:59 UTC (rev 5108)
@@ -1,2 +1,2 @@
-/gccrom/1.2/Wed Apr 4 06:14:39 2007//
D/c////
+/gccrom/1.3/Wed Apr 25 19:45:17 2007//
Modified: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
2007-04-25 18:21:27 UTC (rev 5107)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
2007-04-25 19:52:59 UTC (rev 5108)
@@ -1,2 +1,2 @@
-/aeMB_testbench.c/1.3/Wed Apr 4 14:09:04 2007//
+/aeMB_testbench.c/1.4/Wed Apr 25 19:45:17 2007//
D
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
2007-04-25 18:21:27 UTC (rev 5107)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
2007-04-25 19:52:59 UTC (rev 5108)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_testbench.c,v 1.3 2007/04/04 14:09:04 sybreon Exp $
+ * $Id: aeMB_testbench.c,v 1.4 2007/04/25 22:15:05 sybreon Exp $
*
* AEMB Function Verification C Testbench
* Copyright (C) 2006 Shawn Tan Ser Ngiap <address@hidden>
@@ -28,6 +28,9 @@
*
* HISTORY
* $Log: aeMB_testbench.c,v $
+ * Revision 1.4 2007/04/25 22:15:05 sybreon
+ * Added support for 8-bit and 16-bit data types.
+ *
* Revision 1.3 2007/04/04 14:09:04 sybreon
* Added initial interrupt/exception support.
*
@@ -51,7 +54,7 @@
void int_call_func () {
int *p;
p = 0x88888888;
- *p = 0x00ED557A; // Write a value to a IO port.
+ *p = 0x52544E49; // "INTR"
}
/* Recursive Version */
@@ -82,54 +85,70 @@
return p==a?*(p+2):*(p-1);
}
-/* Compare the Results */
+/* Various Test */
int main() {
unsigned int n;
unsigned int fib_fast, fib_slow;
- unsigned int fib_lut[] = {0,
- 1,
- 1,
- 2,
- 3,
- 5,
- 8,
- 13,
- 21,
- 34,
- 55,
- 89,
- 144,
- 233,
- 377,
- 610,
- 987,
- 1597,
- 2584,
- 4181,
- 6765,
- 10946,
- 17711,
- 28657,
- 46368,
- 75025,
- 121393,
- 196418,
- 317811,
- 514229,
- 832040,
- 1346269,
- 2178309,
- 3524578,
- 5702887};
+ unsigned int fib_lut32[] = {0,
+ 1,
+ 1,
+ 2,
+ 3,
+ 5,
+ 8,
+ 13,
+ 21,
+ 34,
+ 55,
+ 89,
+ 144,
+ 233};
+
+ unsigned short fib_lut16[] = {0,
+ 1,
+ 1,
+ 2,
+ 3,
+ 5,
+ 8,
+ 13,
+ 21,
+ 34,
+ 55,
+ 89,
+ 144,
+ 233};
- for (n=0;n<35;n++) {
+ unsigned char fib_lut8[] = {0,
+ 1,
+ 1,
+ 2,
+ 3,
+ 5,
+ 8,
+ 13,
+ 21,
+ 34,
+ 55,
+ 89,
+ 144,
+ 233};
+
+ for (n=0;n<14;n++) {
fib_slow = slowfib(n);
fib_fast = fastfib(n);
- while ((fib_fast != fib_lut[n]) || (fib_slow != fib_fast)) {
- fib_lut[n] = 0x00ED17FA;
+ while ((fib_slow != fib_fast) ||
+ (fib_fast != fib_lut32[n]) ||
+ (fib_fast != fib_lut16[n]) ||
+ (fib_fast != fib_lut8[n])) {
+ // "FAIL"
+ fib_lut32[n] = 0x4C494146;
}
- }
-
- return fib_fast;
+ // "PASS"
+ fib_lut32[n] = 0x53534150;
+ }
+
+ return 0;
}
+
Modified: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/gccrom
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/gccrom
2007-04-25 18:21:27 UTC (rev 5107)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/gccrom
2007-04-25 19:52:59 UTC (rev 5108)
@@ -1,6 +1,9 @@
#!/bin/sh
-# $Id: gccrom,v 1.2 2007/04/04 06:14:39 sybreon Exp $
+# $Id: gccrom,v 1.3 2007/04/25 22:15:06 sybreon Exp $
# $Log: gccrom,v $
+# Revision 1.3 2007/04/25 22:15:06 sybreon
+# Added support for 8-bit and 16-bit data types.
+#
# Revision 1.2 2007/04/04 06:14:39 sybreon
# Minor changes
#
@@ -11,7 +14,7 @@
mb-gcc -g -mxl-soft-div -mxl-soft-mul -msoft-float -o rom.o $@ && \
mb-objcopy -O binary rom.o rom.bin && \
hexdump -v -e'1/4 "%.8X\n"' rom.bin > ../sim/aeMB.rom && \
-mb-objdump -DSC rom.o > rom.dump && \
+mb-objdump -DSCs rom.o > rom.dump && \
rm rom.bin && \
#mb-run -tv rom.o 2> rom.run && \
echo "ROM generated"
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- [Commit-gnuradio] r5108 - in gnuradio/branches/developers/matt/u2f/opencores/aemb: rtl/verilog rtl/verilog/CVS sim/verilog sim/verilog/CVS sw sw/CVS sw/c sw/c/CVS,
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