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[Commit-gnuradio] r5136 - in gnuradio/branches/developers/thottelt: inba
From: |
thottelt |
Subject: |
[Commit-gnuradio] r5136 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations |
Date: |
Thu, 26 Apr 2007 17:16:50 -0600 (MDT) |
Author: thottelt
Date: 2007-04-26 17:16:49 -0600 (Thu, 26 Apr 2007)
New Revision: 5136
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
Log:
new fifo fixes
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
2007-04-26 23:15:56 UTC (rev 5135)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
2007-04-26 23:16:49 UTC (rev 5136)
@@ -53,12 +53,18 @@
/* Increment fifo_rselect here */
always @(posedge fpga_clock)
begin
+ if (reset)
+ fifo_rselect <= {2**LOG2_N{1'b0}} ;
+
if (fifo_rempty[fifo_rselect])
fifo_rselect <= fifo_rselect + 1 ;
+
+ if (skip_packet)
+ fifo_rselect <= fifo_rselect + 1 ;
end
/* Increment fifo_wselect here */
- always @(posedge usb_clock)
+ always @(posedge usb_clock, reset)
begin
if (reset)
fifo_wselect <= {2**LOG2_N{1'b0}} ;
@@ -67,16 +73,6 @@
fifo_wselect <= fifo_wselect + 1 ;
end
- /* Route skip_packet to the correct fifo_resets signal based on the
fifo_rselect */
- always @(posedge fpga_clock, reset)
- begin
- if (reset)
- fifo_rselect <= {2**LOG2_N{1'b0}} ;
-
- if (skip_packet)
- fifo_rselect <= fifo_rselect + 1 ;
- end
-
/* Generate all the single packet FIFOs */
generate
for( i = 0 ; i < 2**LOG2_N ; i = i + 1 )
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-26
23:15:56 UTC (rev 5135)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-26
23:16:49 UTC (rev 5136)
@@ -253,7 +253,7 @@
Project_File_3 = ./fake_fx2.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177517843 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
11 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177627888 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177628865 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
14 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177272423 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 8
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_6 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
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