[Commit-gnuradio] r5257 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations

[thottelt]

Author: thottelt
Date: 2007-05-08 12:19:08 -0600 (Tue, 08 May 2007)
New Revision: 5257

Modified:
   
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
   
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
   gnuradio/branches/developers/thottelt/simulations/tx.mpf
Log:
tx_empty fixed

Modified: 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
--- 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
        2007-05-08 17:56:34 UTC (rev 5256)
+++ 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
        2007-05-08 18:19:08 UTC (rev 5257)
@@ -34,9 +34,8 @@
     `define TIMESTAMP                4'd3
     `define WAIT                     4'd4
     `define WAITSTROBE               4'd5
-    `define SENDWAIT                 4'd6
-    `define SEND                     4'd7
-    `define DISCARD                  4'd8
+    `define SEND                     4'd6
+    `define DISCARD                  4'd7
 
     /* State registers */
     reg                        [3:0] reader_state;
@@ -77,19 +76,27 @@
                      end
                    else if (burst == 1)
                         underrun <= 1;
+                        
+                   if (tx_strobe == 1)
+                       tx_empty <= 1 ;
                end
 
                              /* Just wait for the fifodata to show up */
                `READ: 
                begin
                    reader_next_state <= `HEADER;
+                   
+                   if (tx_strobe)
+                       tx_empty <= 1 ;
                end
                                
                                   /* Process header */
                `HEADER:
                begin
                    reader_next_state <= `TIMESTAMP;
-                     
+                   if (tx_strobe == 1)
+                       tx_empty <= 1 ;
+                   
                    //Check Start burst flag
                    if (fifodata[3] == 1)
                        burst <= 1;
@@ -105,13 +112,18 @@
 
                `TIMESTAMP: 
                begin
-                     timestamp <= fifodata;
-                     reader_next_state <= `WAIT;
+                   timestamp <= fifodata;
+                   reader_next_state <= `WAIT;
+                   if (tx_strobe == 1)
+                       tx_empty <= 1 ;
                end
                                
                                   // Decide if we wait, send or discard samples
                `WAIT: 
                begin
+                   if (tx_strobe == 1)
+                       tx_empty <= 1 ;
+                   
                    // Wait a little bit more
                    if (timestamp > adc_time + `JITTER)
                        reader_next_state <= `WAIT;        
@@ -136,27 +148,23 @@
                      begin
                        reader_next_state <= `DISCARD;
                        skip <= (payload_len < MAX_PAYLOAD);
-                       tx_empty <= 1 ;
+                       if (tx_strobe == 1)
+                           tx_empty <= 1 ;
                      end  
                    else if (tx_strobe == 1)
                      begin
-                       reader_next_state <= `SENDWAIT;
+                       reader_next_state <= `SEND;
                        rdreq <= 1;
                      end
                end
                
-               `SENDWAIT:
-               begin
-                   reader_next_state <= `SEND; 
-                   rdreq <= 0;
-               end
-               
                                   // Send the samples to the tx_chain
                `SEND:
                begin
                    reader_next_state <= `WAITSTROBE; 
                    read_len <= read_len + 4;
                    tx_empty <= 0;
+                   rdreq <= 0;
                    
                    case(samples_format)
                        `QI16:
@@ -178,6 +186,8 @@
                begin
                    skip <= 0;
                    reader_next_state <= `IDLE;
+                   if (tx_strobe == 1)
+                       tx_empty <= 1 ;
                end
                
                default:

Modified: 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
===================================================================
--- 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
 2007-05-08 17:56:34 UTC (rev 5256)
+++ 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
 2007-05-08 18:19:08 UTC (rev 5257)
@@ -94,12 +94,8 @@
                     WR_chan <= {NUM_CHAN+1{1'b0}} ;
                     
                     /* Notify next block */
-                    case (channel)
-                       `TXCHAN0: done_chan[0] <= 1 ;
-                       `TXCHAN1: done_chan[1] <= 1 ;
-                       `TXCMD:   done_chan[2] <= 1 ;
-                       default:  done_chan[0] <= 1 ;
-                    endcase
+                    done_chan[channel] <= 1 ;
+
                 end
                 else
                     WR_chan[channel] <= 1 ;

Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf    2007-05-08 
17:56:34 UTC (rev 5256)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf    2007-05-08 
18:19:08 UTC (rev 5257)
@@ -255,25 +255,25 @@
 Project_File_4 = ./fake_fx2.v
 Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1178480747 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
11 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_5 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1178645334 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1178647949 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 8 
dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_6 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1178634050 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6 
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1178648314 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6 
dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_7 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
 Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1178634500 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 
cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_8 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
 Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1178234886 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
13 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_9 = ./chan_fifo_readers_test.v
-Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1178644548 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 1 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1178644650 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 
cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_10 = ../inband/usrp/fpga/megacells/fifo_1k.v
 Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1178232565 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 
cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_11 = ./usb_packet_fifo_test.v
 Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177365360 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0 
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_12 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
-Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_12 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1178644305 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 
cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_13 = ./tx_buffer_test.v
-Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1178645641 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3 
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_14 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
-Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1178644305 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1178647009 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_14 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
+Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 
cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_15 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
 Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9 
dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_16 = ./usb_fifo_reader_test.v
@@ -307,6 +307,6 @@
 XML_CustomDoubleClick = 
 LOGFILE_DoubleClick = Edit
 LOGFILE_CustomDoubleClick = 
-EditorState = {tabbed horizontal 1} {Z:/wc/simulations/tx_buffer_test.v 0 1} 
{Z:/wc/simulations/fake_fx2.v 0 0} {Z:/wc/simulations/usb_packet_fifo_test.v 0 
0} {Z:/wc/simulations/chan_fifo_readers_test.v 0 0}
+EditorState = {tabbed horizontal 1} {Z:/wc/simulations/tx_buffer_test.v 0 0} 
{Z:/wc/simulations/fake_fx2.v 0 0} {Z:/wc/simulations/usb_packet_fifo_test.v 0 
1} {Z:/wc/simulations/chan_fifo_readers_test.v 0 0} 
{Z:/wc/inband/usrp/fpga/sdr_lib/strobe_gen.v 0 0} 
{Z:/wc/inband/usrp/fpga/inband_lib/usb_fifo_reader.v 0 0}
 Project_Major_Version = 6
 Project_Minor_Version = 1