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[Commit-gnuradio] r5262 - in gnuradio/branches/developers/matt/u2f/top:
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From: |
matt |
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Subject: |
[Commit-gnuradio] r5262 - in gnuradio/branches/developers/matt/u2f/top: u2_basic u2_fpga u2_sim |
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Date: |
Tue, 8 May 2007 21:38:57 -0600 (MDT) |
Author: matt
Date: 2007-05-08 21:38:56 -0600 (Tue, 08 May 2007)
New Revision: 5262
Modified:
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
gnuradio/branches/developers/matt/u2f/top/u2_sim/BOOTSTRAP.sav
gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v
Log:
reorganized ram_loader interface
Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-05-09 03:37:04 UTC (rev 5261)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-05-09 03:38:56 UTC (rev 5262)
@@ -140,15 +140,15 @@
);
wire ram_loader_done;
- wire ram_loader_rst, processor_rst, wb_rst, dsp_rst;
+ wire ram_loader_rst, wb_rst, dsp_rst;
wire [7:0] sysctrl_dbg;
assign debug = {{dac_a},{dac_b}};
-// assign
debug={{ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,processor_rst,wb_rst,dsp_rst},
- //
{1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached},
- // {sysctrl_dbg},
- // {2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}};
+ // assign
debug={{ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,wb_rst,dsp_rst},
+ //
{1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached},
+ // {sysctrl_dbg},
+ // {2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}};
assign debug_clk[0] = wb_clk;
assign debug_clk[1] = dsp_clk;
@@ -170,65 +170,66 @@
wire m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err,
s5_err, s6_err, s7_err;
wire m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty,
s5_rty, s6_rty, s7_rty;
wire m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we,
s7_we;
- wire m0_cab, m1_cab, s0_cab, s1_cab, s2_cab, s3_cab, s4_cab,
s5_cab, s6_cab, s7_cab;
//////////////////////////////////////////////////////////////////////////////////////////
- // System Controller, handles reset and clocks
- system_control sysctrl (.aux_clk_i(wb_clk),.clk_fpga_i(dsp_clk),
- .dsp_clk_o(),.wb_clk_o(),
-
.ram_loader_rst_o(ram_loader_rst),.processor_rst_o(processor_rst),
- .wb_rst_o(wb_rst),.dsp_rst_o(dsp_rst),
-
.ram_loader_done_i(ram_loader_done),.clock_ready_i(clock_ready),
- .debug_o(sysctrl_dbg) );
-
- /////////////////////////////////////////////////////////////////////
- // Master #0 -- RAM Loader
- ram_loader ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
- // CPLD Interface
- .cfg_clk_i(cpld_clk),
- .cfg_data_i(cpld_din),
- .start_o(cpld_start),
- .mode_o(cpld_mode),
- .done_o(cpld_done),
- .detached_i(cpld_detached),
- // Wishbone Interface
- .wb_dat_o(m0_dat_i),.wb_adr_o(m0_adr[11:0]),
- .wb_stb_o(m0_stb),.wb_cyc_o(m0_cyc),.wb_sel_o(m0_sel),
- .wb_we_o(m0_we),.wb_ack_i(m0_ack),
- .ram_loader_done_o(ram_loader_done));
+ // Reset Controller
+ system_control sysctrl (.wb_clk_i(wb_clk),
+ .ram_loader_rst_o(ram_loader_rst),
+ .wb_rst_o(wb_rst),
+ .ram_loader_done_i(ram_loader_done));
- assign m0_adr[15:12] = 4'h0; // Always talk to RAM, slave #0
- assign m0_cab = 1'b0;
+ // ///////////////////////////////////////////////////////////////////
+ // RAM Loader
+ wire iram_wr_stb, iram_rd_stb, iram_wr_ack, iram_rd_ack, iram_ack,
iram_wr_we;
+ wire [3:0] iram_wr_sel;
+ wire [aw-1:0] iram_wr_adr, iram_rd_adr;
+ wire [dw-1:0] iram_wr_dat, iram_rd_dat;
- //
//////////////////////////////////////////////////////////////////////////////////////////
- // Master # 1 -- Internal processor
+ wire bus_error, proc_int;
- wire iwb_stb, iwb_ack, bus_error, proc_int;
- wire [aw-1:0] iwb_adr;
- wire [dw-1:0] iwb_dat;
-
+ assign iram_rd_ack = ram_loader_done ? iram_ack : 1'b0;
+ assign iram_wr_ack = ram_loader_done ? 1'b0 : iram_ack;
+
+ ram_loader #(.AWIDTH(16))
+ ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
+ // CPLD Interface
+ .cfg_clk_i(cpld_clk),
+ .cfg_data_i(cpld_din),
+ .start_o(cpld_start),
+ .mode_o(cpld_mode),
+ .done_o(cpld_done),
+ .detached_i(cpld_detached),
+ // Wishbone Interface
+ .wb_dat_o(iram_wr_dat),.wb_adr_o(iram_wr_adr),
+ .wb_stb_o(iram_wr_stb),.wb_cyc_o(),.wb_sel_o(iram_wr_sel),
+ .wb_we_o(iram_wr_we),.wb_ack_i(iram_wr_ack),
+ .ram_loader_done_o(ram_loader_done));
+
aeMB_core_BE #(.ISIZ(16),.DSIZ(16))
- aeMB (.sys_clk_i(wb_clk), .sys_rst_i(processor_rst),
+ aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
// Instruction Wishbone bus to I-RAM
- .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
- .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
+ .iwb_stb_o(iram_rd_stb),.iwb_adr_o(iram_rd_adr),
+ .iwb_dat_i(iram_rd_dat),.iwb_ack_i(iram_rd_ack),
// Data Wishbone bus to system bus fabric
-
.dwb_we_o(m1_we),.dwb_stb_o(m1_stb),.dwb_dat_o(m1_dat_i),.dwb_adr_o(m1_adr),
-
.dwb_dat_i(m1_dat_o),.dwb_ack_i(m1_ack),.dwb_sel_o(m1_sel),.dwb_cyc_o(m1_cyc),
+
.dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
+
.dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
// Interrupts and exceptions
.sys_int_i(proc_int),.sys_exc_i(bus_error) );
- assign m1_cab = 1'b0; // Old signal on CONBUS
- assign bus_error = m1_err | m1_rty;
- assign proc_int = 1'b0;
+ assign bus_error = m0_err | m0_rty;
+ assign proc_int = 1'b0;
//
/////////////////////////////////////////////////////////////////////////////////////////
- // Dual Ported RAM -- Slave #0
- // I-port connects directly to processor, D-port connects to bus (slave 0)
+ // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
+ // I-port connects directly to processor and ram loader
- ram_wb_harvard #(.AWIDTH(12))
+ ram_wb_harvard #(.AWIDTH(13))
ID_ram (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
-
.iwb_adr_i(iwb_adr),.iwb_dat_o(iwb_dat),.iwb_stb_i(iwb_stb),.iwb_ack_o(iwb_ack),
+
+ .iwb_adr_i(ram_loader_done ? iram_rd_adr :
iram_wr_adr),.iwb_dat_i(iram_wr_dat),.iwb_dat_o(iram_rd_dat),
+
.iwb_we_i(iram_wr_we),.iwb_ack_o(iram_ack),.iwb_stb_i(ram_loader_done ?
iram_rd_stb : iram_wr_stb),
+ .iwb_sel_i(ram_loader_done ? 4'b1111 : iram_wr_sel),
+
.dwb_adr_i(s0_adr),.dwb_dat_i(s0_dat_o),.dwb_dat_o(s0_dat_i),
.dwb_we_i(s0_we),.dwb_ack_o(s0_ack),.dwb_stb_i(s0_stb),.dwb_sel_i(s0_sel));
@@ -302,36 +303,31 @@
assign s4_rty = 1'b0;
//////////////////////////////////////////////////////////////////////////////////////////////////
- // Wishbone Shared Bus
- wb_conbus_top #(.s0_addr_w(4),.s0_addr(4'h0),.s1_addr_w(4),.s1_addr(4'h1),
- .s27_addr_w(4),.s2_addr(4'h2),.s3_addr(4'h3),.s4_addr(4'h4),
- .s5_addr(4'h5),.s6_addr(4'h6),.s7_addr(4'h7),
- .dw(dw),.aw(aw),.sw(sw)) wb_conbus_top
+ // Wishbone Single Master INTERCON
+ wb_1master #(.s0_addr_w(3),.s0_addr(3'b000),.s1_addr_w(3),.s1_addr(3'h1),
+ .s27_addr_w(3),.s2_addr(3'h2),.s3_addr(3'h3),.s4_addr(3'h4),
+ .s5_addr(3'h5),.s6_addr(3'h6),.s7_addr(3'h7),
+ .dw(dw),.aw(aw),.sw(sw)) wb_1master
(.clk_i(wb_clk),.rst_i(wb_rst),
.m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
-
.m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),.m0_cab_i(m0_cab),
-
.m1_dat_o(m1_dat_o),.m1_ack_o(m1_ack),.m1_err_o(m1_err),.m1_rty_o(m1_rty),.m1_dat_i(m1_dat_i),
-
.m1_adr_i(m1_adr),.m1_sel_i(m1_sel),.m1_we_i(m1_we),.m1_cyc_i(m1_cyc),.m1_stb_i(m1_stb),.m1_cab_i(m1_cab),
-
-
.m2_cyc_i(1'b0),.m3_cyc_i(1'b0),.m4_cyc_i(1'b0),.m5_cyc_i(1'b0),.m6_cyc_i(1'b0),.m7_cyc_i(1'b0),
-
.m2_stb_i(1'b0),.m3_stb_i(1'b0),.m4_stb_i(1'b0),.m5_stb_i(1'b0),.m6_stb_i(1'b0),.m7_stb_i(1'b0),
+
.m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
.s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o
(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
-
.s0_cab_o(s0_cab),.s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty),
+
.s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty),
.s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o
(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
-
.s1_cab_o(s1_cab),.s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty),
+
.s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty),
.s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o
(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
-
.s2_cab_o(s2_cab),.s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty),
+
.s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty),
.s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o
(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
-
.s3_cab_o(s3_cab),.s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty),
+
.s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty),
.s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o
(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
-
.s4_cab_o(s4_cab),.s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty),
+
.s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty),
.s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o
(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
-
.s5_cab_o(s5_cab),.s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty),
+
.s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty),
.s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o
(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
-
.s6_cab_o(s6_cab),.s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty),
+
.s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty),
.s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o
(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
-
.s7_cab_o(s7_cab),.s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty)
+ .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty)
);
assign s6_ack = 1'b0;
@@ -342,9 +338,8 @@
assign s7_err = 1'b0;
assign s7_rty = 1'b0;
assign s7_dat_i = 32'd0;
-
-
- // DSP
+
+ // DSP, Slave #5
reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1,
adc_ovf_b_reg2;
@@ -371,8 +366,7 @@
assign s5_err = 1'b0;
assign s5_rty = 1'b0;
-
-
+
endmodule // u2_basic
// Local Variables:
Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
===================================================================
(Binary files differ)
Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
2007-05-09 03:37:04 UTC (rev 5261)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
2007-05-09 03:38:56 UTC (rev 5262)
@@ -307,6 +307,6 @@
NET "RAM_CE1n" TNM_NET = "RAM_CE1n";
TIMESPEC "TS_RAM_CE1n" = PERIOD "RAM_CE1n" 40 ns HIGH 50 %;
NET "wb_clk" TNM_NET = "wb_clk";
-TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" "TS_dsp_clk" * 2;
+TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" "TS_dsp_clk" * 3;
NET "cpld_clk" TNM_NET = "cpld_clk";
TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
2007-05-09 03:37:04 UTC (rev 5261)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
2007-05-09 03:38:56 UTC (rev 5262)
@@ -196,7 +196,7 @@
.PSDONE(),
.STATUS());
defparam DCM_INST.CLK_FEEDBACK = "1X";
- defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+ defparam DCM_INST.CLKDV_DIVIDE = 3.0;
defparam DCM_INST.CLKFX_DIVIDE = 1;
defparam DCM_INST.CLKFX_MULTIPLY = 4;
defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
Modified: gnuradio/branches/developers/matt/u2f/top/u2_sim/BOOTSTRAP.sav
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_sim/BOOTSTRAP.sav
2007-05-09 03:37:04 UTC (rev 5261)
+++ gnuradio/branches/developers/matt/u2f/top/u2_sim/BOOTSTRAP.sav
2007-05-09 03:38:56 UTC (rev 5262)
@@ -1,6 +1,6 @@
[size] 1400 971
[pos] -1 -1
-*-17.028666 3528125000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 -1 -1 -1 -1
+*-26.028666 3485926000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 -1 -1 -1 -1
@28
u2_sim_top.cpld_clk
u2_sim_top.cpld_detached
@@ -11,18 +11,9 @@
u2_sim_top.clk_fpga
u2_sim_top.clk_sel[1:0]
u2_sim_top.clk_en[1:0]
-u2_sim_top.u2_basic.processor_rst
u2_sim_top.u2_basic.ram_loader_rst
u2_sim_top.u2_basic.wb_rst
-u2_sim_top.u2_basic.sysctrl.dsp_clk_o
-u2_sim_top.u2_basic.sysctrl.gate_dsp_clk
-u2_sim_top.u2_basic.sysctrl.half_clk
address@hidden
-u2_sim_top.u2_basic.sysctrl.wb_clk_o
address@hidden
u2_sim_top.u2_basic.sysctrl.POR
-u2_sim_top.u2_basic.sysctrl.clock_ready_i
-u2_sim_top.u2_basic.sysctrl.start
u2_sim_top.u2_basic.sysctrl.ram_loader_done_i
u2_sim_top.cpld_model.sclk
u2_sim_top.cpld_model.start
@@ -47,7 +38,6 @@
u2_sim_top.u2_basic.shared_spi.wb_dat_o[31:0]
u2_sim_top.u2_basic.shared_spi.rx[127:0]
@28
-u2_sim_top.sdi
u2_sim_top.u2_basic.control_lines.wb_stb_i
u2_sim_top.u2_basic.control_lines.wb_we_i
@22
@@ -58,3 +48,35 @@
u2_sim_top.u2_basic.control_lines.wb_cyc_i
@22
u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0]
address@hidden
+u2_sim_top.clock_ready
+u2_sim_top.u2_basic.ram_loader.done_o
+u2_sim_top.u2_basic.dsp_rst
+u2_sim_top.u2_basic.ram_loader_rst
+u2_sim_top.u2_basic.wb_rst
address@hidden
+u2_sim_top.u2_basic.ID_ram.dwb_adr_i[12:0]
address@hidden
+u2_sim_top.u2_basic.aeMB.iwb_ack_i
+u2_sim_top.u2_basic.ram_loader_done
address@hidden
+u2_sim_top.u2_basic.iram_rd_adr[15:0]
+u2_sim_top.u2_basic.iram_rd_dat[31:0]
address@hidden
+u2_sim_top.u2_basic.iram_wr_we
+u2_sim_top.u2_basic.iram_wr_stb
address@hidden
+u2_sim_top.u2_basic.iram_wr_sel[3:0]
+u2_sim_top.u2_basic.iram_wr_dat[31:0]
+u2_sim_top.u2_basic.iram_wr_adr[15:0]
address@hidden
+u2_sim_top.u2_basic.ram_loader.ram_loader_done_o
+u2_sim_top.u2_basic.ID_ram.dwb_we_i
+u2_sim_top.u2_basic.ID_ram.iwb_we_i
+u2_sim_top.u2_basic.ram_loader.ram_we
+u2_sim_top.u2_basic.ram_loader.ram_we_q
+u2_sim_top.u2_basic.ram_loader.ram_we_s
+u2_sim_top.u2_basic.ram_loader.wb_ack_i
+u2_sim_top.u2_basic.ID_ram.iwb_ack_o
+u2_sim_top.u2_basic.ID_ram.iwb_stb_i
+u2_sim_top.u2_basic.ID_ram.wb_rst_i
Modified: gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v
2007-05-09 03:37:04 UTC (rev 5261)
+++ gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v
2007-05-09 03:38:56 UTC (rev 5262)
@@ -114,17 +114,34 @@
wire [15:0] io_rx;
wire wb_clk, wb_rst;
- wire start;
+ wire start, clock_ready;
reg aux_clk;
-
+
initial aux_clk= 1'b0;
always #25 aux_clk = ~aux_clk;
initial clk_fpga = 1'bx;
initial #3007 clk_fpga = 1'b0;
always #7 clk_fpga = ~clk_fpga;
+
+
+ wire div_clk;
+ reg [2:0] div_ctr = 0;
+ always @(posedge clk_fpga or negedge clk_fpga)
+ if(div_ctr==5)
+ div_ctr = 0;
+ else
+ div_ctr = div_ctr + 1;
+ assign div_clk = (div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2);
+
+ assign dsp_clk = clk_fpga;
+ assign wb_clk = clock_ready ? div_clk : aux_clk;
+
+ initial
+ $monitor($time, ,clock_ready);
+
initial begin
$dumpfile("u2_sim_top.vcd");
$dumpvars(0,u2_sim_top);
@@ -136,8 +153,9 @@
cpld_model
(.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done),
.dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached));
- u2_basic u2_basic(.clk_fpga (clk_fpga),
- .aux_clk (aux_clk),
+ u2_basic u2_basic(.dsp_clk (dsp_clk),
+ .wb_clk (wb_clk),
+ .clock_ready (clock_ready),
.clk_to_mac (clk_to_mac),
.pps_in (pps_in),
.led1 (led1),
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- [Commit-gnuradio] r5262 - in gnuradio/branches/developers/matt/u2f/top: u2_basic u2_fpga u2_sim,
matt <=