[Commit-gnuradio] r5456 - gnuradio/branches/developers/matt/u2f/top/u2_fpga

[matt]

Author: matt
Date: 2007-05-10 21:05:17 -0600 (Thu, 10 May 2007)
New Revision: 5456

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
Log:
working serdes loopback test



Property changes on: gnuradio/branches/developers/matt/u2f/top/u2_fpga
___________________________________________________________________
Name: svn:ignore
   - _ngo
_xmsgs
*.bit
*.stx
*.par
*.unroutes
*.ntrc_log
*.ngr
*.mrp
*.html
*.lso
*.twr
*.bld
*.ncd
*.txt
*.cmd_log
*.drc
*.map
*.twr
*.xml
*.syr
*.ngm
*.xst
*.csv
*.html
*.lock
*.ncd
*.twx
*.ise_ISE_Backup
*.xml
*.ut
*.xpi
*.ngd
*.ncd
*.pad
*.bgn
*.ngc
*.pcf
*.ngd
xst

   + _ngo
_xmsgs
*.bit
*.stx
*.par
*.unroutes
*.ntrc_log
*.ngr
*.mrp
*.html
*.lso
*.twr
*.bld
*.ncd
*.txt
*.cmd_log
*.drc
*.map
*.twr
*.xml
*.syr
*.ngm
*.xst
*.csv
*.html
*.lock
*.ncd
*.twx
*.ise_ISE_Backup
*.xml
*.ut
*.xpi
*.ngd
*.ncd
*.pad
*.bgn
*.ngc
*.pcf
*.ngd
xst
*.log


Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
===================================================================
(Binary files differ)

Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf       
2007-05-01 02:27:46 UTC (rev 5455)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf       
2007-05-11 03:05:17 UTC (rev 5456)
@@ -302,11 +302,14 @@
 #PACE: Start of PACE Area Constraints
 #PACE: Start of PACE Prohibit Constraints
 #PACE: End of Constraints generated by PACE
-NET "dsp_clk" TNM_NET = "dsp_clk";
-TIMESPEC "TS_dsp_clk" = PERIOD "dsp_clk" 10 ns HIGH 50 %;
+NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
 NET "RAM_CE1n" TNM_NET = "RAM_CE1n";
 TIMESPEC "TS_RAM_CE1n" = PERIOD "RAM_CE1n" 40 ns HIGH 50 %;
-NET "wb_clk" TNM_NET = "wb_clk";
-TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" "TS_dsp_clk" * 3;
+#NET "wb_clk" TNM_NET = "wb_clk"
+#TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" "TS_dsp_clk" * 2
 NET "cpld_clk" TNM_NET = "cpld_clk";
+NET "dsp_clk" TNM_NET = "dsp_clk";
 TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+TIMESPEC "TS_aux_to_dsp" = FROM "RAM_CE1n" TO "dsp_clk"  TIG;
+TIMESPEC "TS_dsp_to_aux" = FROM "dsp_clk" TO "RAM_CE1n"  TIG;

Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v     
2007-05-01 02:27:46 UTC (rev 5455)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v     
2007-05-11 03:05:17 UTC (rev 5456)
@@ -65,10 +65,10 @@
    output ser_loopen,
    output ser_rx_en,
    
-   input ser_tx_clk,
-   input [15:0] ser_t,
-   input ser_tklsb,
-   input ser_tkmsb,
+   output ser_tx_clk,
+   output [15:0] ser_t,
+   output ser_tklsb,
+   output ser_tkmsb,
 
    input ser_rx_clk,
    input [15:0] ser_r,
@@ -161,7 +161,7 @@
    wire        aux_clk = RAM_CE1n;   // FIXME  Hacked on with Blue Wire
    wire        cpld_detached = RAM_A[14]; // FIXME  Hacked on with Blue Wire
 
-   wire        clk_fpga, dsp_clk, clk_div2, dcm_out, wb_clk, clock_ready;
+   wire        clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
 
    IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
    defparam    clk_fpga_pin.IOSTANDARD = "LVPECL_25";
@@ -174,6 +174,7 @@
    OBUFDS exp_pps_out_pin 
(.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
    defparam    exp_pps_out_pin.IOSTANDARD = "LVDS_25";
 
+   wire        dcm_rst = ~clock_ready;
 
    // Handle Clocks
    DCM DCM_INST (.CLKFB(dsp_clk), 
@@ -182,8 +183,8 @@
                  .PSCLK(0), 
                  .PSEN(0), 
                  .PSINCDEC(0), 
-                 .RST(RST_IN), 
-                 .CLKDV(clk_div2), 
+                 .RST(dcm_rst), 
+                 .CLKDV(clk_div), 
                  .CLKFX(), 
                  .CLKFX180(), 
                  .CLK0(dcm_out), 
@@ -211,8 +212,9 @@
    defparam DCM_INST.STARTUP_WAIT = "FALSE";
 
    BUFGMUX wbclk_BUFGMUX (.I0(aux_clk), 
-                          .I1(clk_div2), 
+                          .I1(clk_div), 
                           .S(clock_ready), 
+                          //.S(1'b0), 
                           .O(wb_clk));
 
    BUFG dspclk_BUFG (.I(dcm_out),