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[Commit-gnuradio] r5458 - gnuradio/branches/developers/matt/u2f/control_
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From: |
matt |
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Subject: |
[Commit-gnuradio] r5458 - gnuradio/branches/developers/matt/u2f/control_lib |
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Date: |
Thu, 10 May 2007 21:08:06 -0600 (MDT) |
Author: matt
Date: 2007-05-10 21:08:06 -0600 (Thu, 10 May 2007)
New Revision: 5458
Added:
gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool_tb.v
gnuradio/branches/developers/matt/u2f/control_lib/fifo_reader.v
gnuradio/branches/developers/matt/u2f/control_lib/fifo_writer.v
gnuradio/branches/developers/matt/u2f/control_lib/mux_32_4.v
Modified:
gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
gnuradio/branches/developers/matt/u2f/control_lib/serdes.v
Log:
serdes loopback tester, beginnings of buffer pool system
Modified: gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
2007-05-11 03:06:24 UTC (rev 5457)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
2007-05-11 03:08:06 UTC (rev 5458)
@@ -15,7 +15,7 @@
input wb_rst_i,
input wb_we_i,
input wb_stb_i,
- input [12:0] wb_adr_i,
+ input [15:0] wb_adr_i,
input [31:0] wb_dat_i,
output reg [31:0] wb_dat_o,
output reg wb_ack_o,
@@ -56,48 +56,72 @@
wire [7:0] sel_a;
wire [31:0] buf0_outa, buf1_outa, buf2_outa, buf3_outa, buf4_outa,
buf5_outa, buf6_outa, buf7_outa;
+
+ wire [2:0] which_buf = wb_adr_i[13:11]; // address 15:14 selects the
buffer pool
+ wire [8:0] buf_addr = wb_adr_i[10:2]; // ignore address 1:0
+
+ wire buf0_dir, buf1_dir, buf2_dir, buf3_dir,
+ buf4_dir, buf5_dir, buf6_dir, buf7_dir;
+ wire [1:0] buf0_sel, buf1_sel, buf2_sel, buf3_sel,
+ buf4_sel, buf5_sel, buf6_sel, buf7_sel;
+ wire [8:0] buf0_start, buf1_start, buf2_start, buf3_start,
+ buf4_start, buf5_start, buf6_start, buf7_start;
+ wire [8:0] buf0_end, buf1_end, buf2_end, buf3_end,
+ buf4_end, buf5_end, buf6_end, buf7_end;
decoder_3_8 dec(.sel(wb_adr_i[11:9]),.res(sel_a));
-
+
+ wire [31:0] b0di, b0do, b1di, b1do, b2di, b2do, b3di, b3do,
+ b4di, b4do, b5di, b5do, b6di, b6do, b7di, b7do;
+
+ mux_32_4 m0i(buf0_sel, din_0, din_1, din_2, 32'd0, b0di);
+ mux_32_4 m1i(buf1_sel, din_0, din_1, din_2, 32'd0, b1di);
+ mux_32_4 m2i(buf2_sel, din_0, din_1, din_2, 32'd0, b2di);
+ mux_32_4 m3i(buf3_sel, din_0, din_1, din_2, 32'd0, b3di);
+ mux_32_4 m4i(buf4_sel, din_0, din_1, din_2, 32'd0, b4di);
+ mux_32_4 m5i(buf5_sel, din_0, din_1, din_2, 32'd0, b5di);
+ mux_32_4 m6i(buf6_sel, din_0, din_1, din_2, 32'd0, b6di);
+ mux_32_4 m7i(buf7_sel, din_0, din_1, din_2, 32'd0, b7di);
+
buffer_2k buf_0
(.clka(wb_clk_i),.ena(wb_stb_i & sel_a[0]),.wea(wb_we_i),
.addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf0_outa),
- .clkb(stream_clk),.enb(),.web(),.addrb(),.dib(),.dob());
+ .clkb(stream_clk),.enb(1),.web(),.addrb(b0a),.dib(b0di),.dob(b0do));
buffer_2k buf_1
(.clka(wb_clk_i),.ena(wb_stb_i & sel_a[1]),.wea(wb_we_i),
.addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf1_outa),
- .clkb(stream_clk),.enb(),.web(),.addrb(),.dib(),.dob());
+ .clkb(stream_clk),.enb(1),.web(),.addrb(b1a),.dib(b1di),.dob(b1do));
buffer_2k buf_2
(.clka(wb_clk_i),.ena(wb_stb_i & sel_a[2]),.wea(wb_we_i),
.addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf2_outa),
- .clkb(stream_clk),.enb(),.web(),.addrb(),.dib(),.dob());
+ .clkb(stream_clk),.enb(1),.web(),.addrb(b2a),.dib(b2di),.dob(b2do));
buffer_2k buf_3
(.clka(wb_clk_i),.ena(wb_stb_i & sel_a[3]),.wea(wb_we_i),
.addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf3_outa),
- .clkb(stream_clk),.enb(),.web(),.addrb(),.dib(),.dob());
+ .clkb(stream_clk),.enb(1),.web(),.addrb(b3a),.dib(b3di),.dob(b3do));
buffer_2k buf_4
(.clka(wb_clk_i),.ena(wb_stb_i & sel_a[4]),.wea(wb_we_i),
.addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf4_outa),
- .clkb(stream_clk),.enb(),.web(),.addrb(),.dib(),.dob());
+ .clkb(stream_clk),.enb(1),.web(),.addrb(b4a),.dib(b4di),.dob(b4do));
buffer_2k buf_5
(.clka(wb_clk_i),.ena(wb_stb_i & sel_a[5]),.wea(wb_we_i),
.addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf5_outa),
- .clkb(stream_clk),.enb(),.web(),.addrb(),.dib(),.dob());
+ .clkb(stream_clk),.enb(1),.web(),.addrb(b5a),.dib(b5di),.dob(b5do));
buffer_2k buf_6
(.clka(wb_clk_i),.ena(wb_stb_i & sel_a[6]),.wea(wb_we_i),
.addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf6_outa),
- .clkb(stream_clk),.enb(),.web(),.addrb(),.dib(),.dob());
+ .clkb(stream_clk),.enb(1),.web(),.addrb(b6a),.dib(b6di),.dob(b6do));
buffer_2k buf_7
(.clka(wb_clk_i),.ena(wb_stb_i & sel_a[7]),.wea(wb_we_i),
.addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf7_outa),
- .clkb(stream_clk),.enb(),.web(),.addrb(),.dib(),.dob());
+ .clkb(stream_clk),.enb(1),.web(),.addrb(b7a),.dib(b7di),.dob(b7do));
always @(posedge wb_clk_i)
if(wb_stb_i)
Added: gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool_tb.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool_tb.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool_tb.v
2007-05-11 03:08:06 UTC (rev 5458)
@@ -0,0 +1,87 @@
+
+module buffer_pool_tb();
+
+ wire wb_clk_i;
+ wire wb_rst_i;
+ wire wb_we_i;
+ wire wb_stb_i;
+ wire [15:0] wb_adr_i;
+ wire [31:0] wb_dat_i;
+ wire [31:0] wb_dat_o;
+ wire wb_ack_o;
+ wire wb_err_o;
+
+ wire stream_clk;
+ // Write Interfaces
+ wire [31:0] din_0;
+ wire write_0;
+ wire done_0;
+ wire wr_rdy_0;
+
+ wire [31:0] din_1;
+ wire write_1;
+ wire done_1;
+ wire wr_rdy_1;
+
+ wire [31:0] din_2;
+ wire write_2;
+ wire done_2;
+ wire wr_rdy_2;
+
+ // Read Interfaces
+ wire [31:0] dout_0;
+ wire rd_rdy_0;
+ wire read_0;
+
+ wire [31:0] dout_1;
+ wire rd_rdy_1;
+ wire read_1;
+
+ wire [31:0] dout_2;
+ wire rd_rdy_2;
+ wire read_2;
+
+ buffer_pool dut
+ (.wb_clk_i(),
+ .wb_rst_i(),
+ .wb_we_i(),
+ .wb_stb_i(),
+ .wb_adr_i(),
+ .wb_dat_i(),
+ .wb_dat_o(),
+ .wb_ack_o(),
+ .wb_err_o(),
+
+ .stream_clk(),
+
+ // Write Interfaces
+ .din_0(),
+ .write_0(),
+ .done_0(),
+ .wr_rdy_0(),
+
+ .din_1(),
+ .write_1(),
+ .done_1(),
+ .wr_rdy_1(),
+
+ .din_2(),
+ .write_2(),
+ .done_2(),
+ .wr_rdy_2(),
+
+ // Read Interfaces
+ .dout_0(),
+ .rd_rdy_0(),
+ .read_0(),
+
+ .dout_1(),
+ .rd_rdy_1(),
+ .read_1(),
+
+ .dout_2(),
+ .rd_rdy_2(),
+ .read_2()
+ );
+
+endmodule // buffer_pool_tb
Added: gnuradio/branches/developers/matt/u2f/control_lib/fifo_reader.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/fifo_reader.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/fifo_reader.v
2007-05-11 03:08:06 UTC (rev 5458)
@@ -0,0 +1,27 @@
+
+module fifo_reader
+ #(parameter rate=4)
+ (input clk,
+ input [31:0] data_in,
+ input ready,
+ output read
+ );
+
+ reg [7:0] state = 0;
+
+ always @(posedge clk)
+ if(ready)
+ if(state == rate)
+ state <= 0;
+ else
+ state <= state + 1;
+ else
+ state <= 0;
+
+ assign read = (state == rate);
+
+ initial $monitor(data_in);
+
+endmodule // fifo_reader
+
+
Added: gnuradio/branches/developers/matt/u2f/control_lib/fifo_writer.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/fifo_writer.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/fifo_writer.v
2007-05-11 03:08:06 UTC (rev 5458)
@@ -0,0 +1,31 @@
+
+module fifo_writer
+ #(parameter rate=4)
+ (input clk,
+ output [31:0] data_out,
+ output write,
+ input done,
+ input ready
+ );
+
+ reg [7:0] state = 0;
+
+
+ // FIXME change this to write
+ always @(posedge clk)
+ if(ready)
+ if(state == rate)
+ state <= 0;
+ else
+ state <= state + 1;
+ else
+ state <= 0;
+
+ assign read = (state == rate);
+
+ initial $monitor(data_in);
+
+endmodule // fifo_writer
+
+
+
Added: gnuradio/branches/developers/matt/u2f/control_lib/mux_32_4.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/mux_32_4.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/mux_32_4.v
2007-05-11 03:08:06 UTC (rev 5458)
@@ -0,0 +1,13 @@
+
+
+module mux_32_4
+ (input [1:0] sel,
+ input [31:0] in0,
+ input [31:0] in1,
+ input [31:0] in2,
+ input [31:0] in3,
+ output [31:0] out);
+
+ assign out = sel[1] ? (sel[0] ? in3 : in2) : (sel[0] ? in1 : in0);
+
+endmodule // mux_32_4
Modified: gnuradio/branches/developers/matt/u2f/control_lib/serdes.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes.v 2007-05-11
03:06:24 UTC (rev 5457)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes.v 2007-05-11
03:08:06 UTC (rev 5458)
@@ -1,13 +1,34 @@
+// SERDES Interface
+
+// LS-Byte is sent first, MS-Byte is second
+// Invalid K Codes
+// K0.0 000-00000 Error detected
+// K31.7 111-11111 Loss of input signal
+
+// Valid K Codes
+// K28.0 000-11100
+// K28.1 001-11100 Alternate COMMA?
+// K28.2 010-11100
+// K28.3 011-11100
+// K28.4 100-11100
+// K28.5 101-11100 Standard COMMA?
+// K28.6 110-11100
+// K28.7 111-11100 Bad COMMA?
+// K23.7 111-10111
+// K27.7 111-11011
+// K29.7 111-11101
+// K30.7 111-11110
+
module serdes
(input clk,
input rst,
// TX HW Interface
output ser_tx_clk,
- output [15:0] ser_t,
- output ser_tklsb,
- output ser_tkmsb,
+ output reg [15:0] ser_t,
+ output reg ser_tklsb,
+ output reg ser_tkmsb,
// RX HW Interface
input ser_rx_clk,
@@ -16,24 +37,96 @@
input ser_rkmsb,
// TX Stream Interface
- input [31:0] dout_0,
- input rd_rdy_0,
- output read_0,
+ input [31:0] dout,
+ input rd_rdy,
+ output read,
// RX Stream Interface
- output [31:0] din_0,
- output write_0,
- output done_0,
- input wr_rdy_0,
+ output [31:0] din,
+ output write,
+ output done,
+ input wr_rdy
+ );
- // HW controls -- FIXME -- maybe these should be controlled by the
processor directly.
+ localparam COMMA = 8'b101_11100; // K28.5
+ //localparam IDLE = 8'b001_11100; // K28.1
+ localparam PKT_START = 8'b110_11100; // K28.6
+ localparam PKT_END = 8'b100_11100; // K28.4
+ localparam LOS = 8'b111_11111; // K31.7
+ localparam ERROR = 8'b000_00000; // K0.0
- output ser_enable,
- output ser_prbsen,
- output ser_loopen,
- output ser_rx_en
- );
+ assign ser_tx_clk = clk;
+
+ localparam IDLE = 3'd0;
+ localparam START = 3'd1;
+ localparam RUN = 3'd2;
+ localparam RESTART = 3'd3;
+ localparam ON_ERROR = 3'd4;
+
+ reg [2:0] state, next_state;
+
+ reg [7:0] counter;
+
+ reg rcv_comma, rcv_comma_ret, rcv_error, rcv_error_ret;
+ always @(posedge clk)
+ if(rst)
+ begin
+ state <= IDLE;
+ counter <= 0;
+ end
+ else
+ case(state)
+ IDLE :
+ if(rcv_comma_ret)
+ state <= START;
+ START :
+ begin
+ counter <= 0;
+ state <= RUN;
+ end
+ RUN :
+ if(rcv_error_ret)
+ state <= ON_ERROR;
+ else if(counter == 8'd234)
+ state <= RESTART;
+ else
+ counter <= counter + 8'd1;
+ RESTART:
+ state <= START;
+ ON_ERROR :
+ state <= IDLE;
+ default
+ state <= IDLE;
+ endcase // case(state)
+
+ always @(posedge clk)
+ case(state)
+ IDLE :
+ {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,COMMA,COMMA};
+ START :
+ {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,PKT_START,COMMA};
+ RUN :
+ {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,~counter,counter};
+ RESTART :
+ {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,PKT_END,8'd235};
+ ON_ERROR :
+ {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,COMMA,COMMA};
+ endcase // case(state)
+
+ always @(posedge ser_rx_clk)
+ rcv_comma <= (ser_rkmsb & (ser_r[15:8] == COMMA)) ||
+ (ser_rklsb & (ser_r[7:0] == COMMA));
+
+ always @(posedge clk)
+ rcv_comma_ret <= rcv_comma;
+
+ always @(posedge ser_rx_clk)
+ rcv_error <= (ser_rkmsb & ser_rklsb & ((ser_r[7:0] == LOS)||(ser_r[7:0]
== ERROR));
+
+ always @(posedge clk)
+ rcv_error_ret <= rcv_error;
+
+ assign din =
{counter,rcv_comma,state[2:0],ser_tkmsb,ser_tklsb,ser_rkmsb,ser_rklsb,ser_r[15:0]};
-
endmodule // serdes
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