[Commit-gnuradio] r5472 - gnuradio/branches/developers/matt/u2f/sdr_lib

[matt]

Author: matt
Date: 2007-05-14 20:51:01 -0600 (Mon, 14 May 2007)
New Revision: 5472

Added:
   gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v
   gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v
Removed:
   gnuradio/branches/developers/matt/u2f/sdr_lib/setting_reg.v
Modified:
   gnuradio/branches/developers/matt/u2f/sdr_lib/cordic.v
   gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core.v
Log:
split dsp_core to tx and rx, modified cordic with parameters instead of defines


Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/cordic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/cordic.v      2007-05-15 
02:49:17 UTC (rev 5471)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/cordic.v      2007-05-15 
02:51:01 UTC (rev 5472)
@@ -2,7 +2,7 @@
 //
 //  USRP - Universal Software Radio Peripheral
 //
-//  Copyright (C) 2003 Matt Ettus
+//  Copyright (C) 2003, 2007 Matt Ettus
 //
 //  This program is free software; you can redistribute it and/or modify
 //  it under the terms of the GNU General Public License as published by
@@ -43,24 +43,24 @@
    // Compute consts.  Would be easier if vlog had atan...
    // see gen_cordic_consts.py
    
-`define c00 16'd8192
-`define c01 16'd4836
-`define c02 16'd2555
-`define c03 16'd1297
-`define c04 16'd651
-`define c05 16'd326
-`define c06 16'd163
-`define c07 16'd81
-`define c08 16'd41
-`define c09 16'd20
-`define c10 16'd10
-`define c11 16'd5
-`define c12 16'd3
-`define c13 16'd1
-`define c14 16'd1
-`define c15 16'd0
-`define c16 16'd0
-
+   localparam         c00 = 16'd8192;
+   localparam         c01 = 16'd4836;
+   localparam         c02 = 16'd2555;
+   localparam         c03 = 16'd1297;
+   localparam         c04 = 16'd651;
+   localparam         c05 = 16'd326;
+   localparam         c06 = 16'd163;
+   localparam         c07 = 16'd81;
+   localparam         c08 = 16'd41;
+   localparam         c09 = 16'd20;
+   localparam         c10 = 16'd10;
+   localparam         c11 = 16'd5;
+   localparam         c12 = 16'd3;
+   localparam         c13 = 16'd1;
+   localparam         c14 = 16'd1;
+   localparam         c15 = 16'd0;
+   localparam         c16 = 16'd0;
+   
    always @(posedge clock)
      if(reset)
        begin
@@ -86,18 +86,18 @@
    // FIXME need to handle variable number of stages
    // FIXME should be able to narrow zwidth but quartus makes it bigger...
    // This would be easier if arrays worked better in vlog...
-   cordic_stage #(bitwidth+2,zwidth-1,0) cordic_stage0 
(clock,reset,enable,x0,y0,z0,`c00,x1,y1,z1);
-   cordic_stage #(bitwidth+2,zwidth-1,1) cordic_stage1 
(clock,reset,enable,x1,y1,z1,`c01,x2,y2,z2);
-   cordic_stage #(bitwidth+2,zwidth-1,2) cordic_stage2 
(clock,reset,enable,x2,y2,z2,`c02,x3,y3,z3);
-   cordic_stage #(bitwidth+2,zwidth-1,3) cordic_stage3 
(clock,reset,enable,x3,y3,z3,`c03,x4,y4,z4);
-   cordic_stage #(bitwidth+2,zwidth-1,4) cordic_stage4 
(clock,reset,enable,x4,y4,z4,`c04,x5,y5,z5);
-   cordic_stage #(bitwidth+2,zwidth-1,5) cordic_stage5 
(clock,reset,enable,x5,y5,z5,`c05,x6,y6,z6);
-   cordic_stage #(bitwidth+2,zwidth-1,6) cordic_stage6 
(clock,reset,enable,x6,y6,z6,`c06,x7,y7,z7);
-   cordic_stage #(bitwidth+2,zwidth-1,7) cordic_stage7 
(clock,reset,enable,x7,y7,z7,`c07,x8,y8,z8);
-   cordic_stage #(bitwidth+2,zwidth-1,8) cordic_stage8 
(clock,reset,enable,x8,y8,z8,`c08,x9,y9,z9);
-   cordic_stage #(bitwidth+2,zwidth-1,9) cordic_stage9 
(clock,reset,enable,x9,y9,z9,`c09,x10,y10,z10);
-   cordic_stage #(bitwidth+2,zwidth-1,10) cordic_stage10 
(clock,reset,enable,x10,y10,z10,`c10,x11,y11,z11);
-   cordic_stage #(bitwidth+2,zwidth-1,11) cordic_stage11 
(clock,reset,enable,x11,y11,z11,`c11,x12,y12,z12);
+   cordic_stage #(bitwidth+2,zwidth-1,0) cordic_stage0 
(clock,reset,enable,x0,y0,z0,c00,x1,y1,z1);
+   cordic_stage #(bitwidth+2,zwidth-1,1) cordic_stage1 
(clock,reset,enable,x1,y1,z1,c01,x2,y2,z2);
+   cordic_stage #(bitwidth+2,zwidth-1,2) cordic_stage2 
(clock,reset,enable,x2,y2,z2,c02,x3,y3,z3);
+   cordic_stage #(bitwidth+2,zwidth-1,3) cordic_stage3 
(clock,reset,enable,x3,y3,z3,c03,x4,y4,z4);
+   cordic_stage #(bitwidth+2,zwidth-1,4) cordic_stage4 
(clock,reset,enable,x4,y4,z4,c04,x5,y5,z5);
+   cordic_stage #(bitwidth+2,zwidth-1,5) cordic_stage5 
(clock,reset,enable,x5,y5,z5,c05,x6,y6,z6);
+   cordic_stage #(bitwidth+2,zwidth-1,6) cordic_stage6 
(clock,reset,enable,x6,y6,z6,c06,x7,y7,z7);
+   cordic_stage #(bitwidth+2,zwidth-1,7) cordic_stage7 
(clock,reset,enable,x7,y7,z7,c07,x8,y8,z8);
+   cordic_stage #(bitwidth+2,zwidth-1,8) cordic_stage8 
(clock,reset,enable,x8,y8,z8,c08,x9,y9,z9);
+   cordic_stage #(bitwidth+2,zwidth-1,9) cordic_stage9 
(clock,reset,enable,x9,y9,z9,c09,x10,y10,z10);
+   cordic_stage #(bitwidth+2,zwidth-1,10) cordic_stage10 
(clock,reset,enable,x10,y10,z10,c10,x11,y11,z11);
+   cordic_stage #(bitwidth+2,zwidth-1,11) cordic_stage11 
(clock,reset,enable,x11,y11,z11,c11,x12,y12,z12);
 
    assign xo = x12[bitwidth:1];  
    assign yo = y12[bitwidth:1];

Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core.v    2007-05-15 
02:49:17 UTC (rev 5471)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core.v    2007-05-15 
02:51:01 UTC (rev 5472)
@@ -50,7 +50,6 @@
 
    wire         signed [15:0]   da, db;
    reg                  signed [15:0]   dar, dbr;
-   reg                  signed [35:0] prod_i, prod_q;
    
    cordic cordic(.clock(dsp_clk), 
                 .reset(dsp_rst),
@@ -58,6 +57,27 @@
                 .xi(i),.yi(q),.zi(phase[31:16]),
                 .xo(da),.yo(db),.zo() );
 
+   wire                 signed [35:0] prod_i, prod_q;
+/* MULT18X18S MULT18X18S_inst (
+      .P(prod_i),    // 36-bit multiplier output
+      .A({{2{da[15]}},da} ),    // 18-bit multiplier input
+      .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
+      .C(dsp_clk),    // Clock input
+      .CE(1'b1),  // Clock enable input
+      .R(dsp_rst)     // Synchronous reset input
+   );
+MULT18X18S MULT18X18S_inst_2 (
+      .P(prod_q),    // 36-bit multiplier output
+      .A({{2{db[15]}},da} ),    // 18-bit multiplier input
+      .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
+      .C(dsp_clk),    // Clock input
+      .CE(1'b1),  // Clock enable input
+      .R(dsp_rst)     // Synchronous reset input
+   );
+  */ 
+   /*
+   reg                  signed [35:0] prod_i, prod_q;
+
    always @(posedge dsp_clk)
      if(dsp_rst)
        prod_i <= 36'sd0;
@@ -69,6 +89,7 @@
        prod_q <= 36'sd0;
      else
        prod_q <= {{2{db[15]}},db} * {{2{scale_q[15]}},scale_q};
+*/
 
    always @(posedge dsp_clk)
      dac_a <= prod_i[23:8];

Added: gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v                 
        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v 2007-05-15 
02:51:01 UTC (rev 5472)
@@ -0,0 +1,45 @@
+
+module dsp_core_rx
+  (input clk, input rst,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+   input [13:0] adc_a, input adc_ovf_a,
+   input [13:0] adc_b, input adc_ovf_b,
+   
+   output [31:0] rx_dat_o,
+   output rx_write_o,
+   output rx_done_o,
+   input rx_ready_i,
+   input rx_full_i
+   );
+
+   wire [15:0] scale_i, scale_q;
+   wire [31:0] phase_inc;
+   reg [31:0]  phase;
+   
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else
+       phase <= phase + phase_inc;
+
+   wire [23:0] i_bb, q_bb;
+   
+   cordic #(.bitwidth(24))
+     cordic(.clock(clk), .reset(rst), .enable(1'b1),
+           .xi({adc_a,10'b0}),. yi({adc_b,10'b0}), .zi(phase[31:16]),
+           .xo(i_bb),.yo(q_bb),.zo() );
+
+   cic_decim #(.bw(24))
+     decim_i (.clock(clk),.reset(rst),.enable(1'b1),
+             .rate(),.strobe_in(1'b1),.strobe_out(decim_strobe),
+             .signal_in(),.signal_out());
+   
+   cic_decim_shifter #(.bw_in(),.bw_out())
+     cds_i (.clock(clk),.reset(rst),.enable(1),.sig_in(),.sig_out());
+
+   MULT18X18S mult_i
+     (.P(prod_i),.A({{2{da[15]}},da} ),.B({{2{scale_i[15]}},scale_i}),
+      .C(dsp_clk),.CE(1'b1),.R(dsp_rst) );
+   
+endmodule // dsp_core_rx

Added: gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v                 
        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v 2007-05-15 
02:51:01 UTC (rev 5472)
@@ -0,0 +1,100 @@
+
+module dsp_core 
+  (input wb_clk_i,
+   input wb_rst_i,
+   input wb_stb_i,
+   input wb_we_i,
+   input [15:0] wb_adr_i,
+   input [3:0] wb_sel_i,
+   input [31:0] wb_dat_i,
+   output [31:0] wb_dat_o,
+   output wb_ack_o,
+   
+   input dsp_clk,
+   input dsp_rst,
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output reg [15:0] dac_a,
+   output reg [15:0] dac_b
+   );
+
+   assign       wb_dat_o = 32'd0;  // No readback for now
+
+   wire [15:0]          i, q, scale_i, scale_q;
+   wire [31:0]          phase_inc;
+   reg [31:0]   phase;
+   
+   wb_regfile_2clock
+     regs (.wb_clk_i(wb_clk_i),.wb_rst_i(wb_rst_i),
+          .wb_stb_i(wb_stb_i),.wb_we_i(wb_we_i),
+          .wb_adr_i(wb_adr_i),.wb_dat_i(wb_dat_i),
+          .wb_sel_i(wb_sel_i),.wb_ack_o(wb_ack_o),
+          .alt_clk(dsp_clk),.alt_rst(dsp_rst),
+          .reg00({i,q}),
+          .reg01(phase_inc),
+          .reg02({scale_i,scale_q}),
+          .reg03(),
+          .reg04(),
+          .reg05(),
+          .reg06(),
+          .reg07()
+          );
+
+   always @(posedge dsp_clk)
+     if(dsp_rst)
+       phase <= 0;
+     else
+       phase <= phase + phase_inc;
+
+   wire         signed [15:0]   da, db;
+   reg                  signed [15:0]   dar, dbr;
+   
+   cordic cordic(.clock(dsp_clk), 
+                .reset(dsp_rst),
+                .enable(1'b1),
+                .xi(i),.yi(q),.zi(phase[31:16]),
+                .xo(da),.yo(db),.zo() );
+
+   wire                 signed [35:0] prod_i, prod_q;
+/* MULT18X18S MULT18X18S_inst (
+      .P(prod_i),    // 36-bit multiplier output
+      .A({{2{da[15]}},da} ),    // 18-bit multiplier input
+      .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
+      .C(dsp_clk),    // Clock input
+      .CE(1'b1),  // Clock enable input
+      .R(dsp_rst)     // Synchronous reset input
+   );
+MULT18X18S MULT18X18S_inst_2 (
+      .P(prod_q),    // 36-bit multiplier output
+      .A({{2{db[15]}},da} ),    // 18-bit multiplier input
+      .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
+      .C(dsp_clk),    // Clock input
+      .CE(1'b1),  // Clock enable input
+      .R(dsp_rst)     // Synchronous reset input
+   );
+  */ 
+   /*
+   reg                  signed [35:0] prod_i, prod_q;
+
+   always @(posedge dsp_clk)
+     if(dsp_rst)
+       prod_i <= 36'sd0;
+     else
+       prod_i <= {{2{da[15]}},da} * {{2{scale_i[15]}},scale_i};
+
+   always @(posedge dsp_clk)
+     if(dsp_rst)
+       prod_q <= 36'sd0;
+     else
+       prod_q <= {{2{db[15]}},db} * {{2{scale_q[15]}},scale_q};
+*/
+
+   always @(posedge dsp_clk)
+     dac_a <= prod_i[23:8];
+
+   always @(posedge dsp_clk)
+     dac_b <= prod_q[23:8];
+   
+endmodule // dsp_core

Deleted: gnuradio/branches/developers/matt/u2f/sdr_lib/setting_reg.v