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[Commit-gnuradio] r5797 - in gnuradio/branches/developers/thottelt: inba
|
From: |
thottelt |
|
Subject: |
[Commit-gnuradio] r5797 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/toplevel/usrp_inband_usb simulations simulations/work |
|
Date: |
Tue, 19 Jun 2007 09:53:01 -0600 (MDT) |
Author: thottelt
Date: 2007-06-19 09:53:00 -0600 (Tue, 19 Jun 2007)
New Revision: 5797
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/packet_builder.v
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
gnuradio/branches/developers/thottelt/simulations/rx_fake_fx2.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
gnuradio/branches/developers/thottelt/simulations/work/_info
Log:
rx coded but not working yet
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/packet_builder.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/packet_builder.v
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/packet_builder.v
2007-06-19 15:53:00 UTC (rev 5797)
@@ -0,0 +1,112 @@
+module packet_builder #(parameter NUM_CHAN = 2) (
+ // System
+ input rxclk,
+ input reset,
+ // ADC side
+ input [15:0]chan_fifodata,
+ input [NUM_CHAN:0]chan_empty,
+ input [9:0]chan_usedw,
+ output reg [NUM_CHAN:0]rd_select,
+ output reg [NUM_CHAN:0]chan_rdreq,
+ // FX2 side
+ output reg WR,
+ output reg [15:0]fifodata,
+ input have_space );
+
+ parameter IDLE = 0;
+ parameter HEADER1 = 1;
+ parameter HEADER2 = 2;
+ parameter TIMESTAMP = 3;
+ parameter FORWARD = 4;
+
+ `define MAXPAYLOAD 504
+
+ `define PAYLOAD_LEN 8:0
+ `define TAG 12:9
+ `define MBZ 15:13
+
+ `define CHAN 4:0
+ `define RSSI 10:5
+ `define BURST 12:11
+ `define DROPPED 13
+ `define UNDERRUN 14
+ `define OVERRUN 15
+
+ reg [3:0] state;
+ reg [8:0] read_length;
+ reg [8:0] payload_len;
+ reg tstamp_complete;
+
+ always @(posedge rxclk)
+ begin
+ if (reset)
+ begin
+ WR <= 0;
+ rd_select <= 0;
+ chan_rdreq <= 0;
+ tstamp_complete <= 0;
+ state <= IDLE;
+ end
+ else case (state)
+ IDLE: begin
+ rd_select[0] <= 1;
+
+ if (~chan_empty[0] && have_space)
+ state <= HEADER1;
+ end
+
+ HEADER1: begin
+ fifodata[`PAYLOAD_LEN] <= (chan_usedw > 9'd252
+ ? 9'd252 : chan_usedw << 1);
+ payload_len <= (chan_usedw > 9'd252
+ ? 9'd252 : chan_usedw << 1);
+ fifodata[`TAG] <= 0;
+ fifodata[`MBZ] <= 0;
+ WR <= 1;
+
+ state <= HEADER2;
+ read_length <= 0;
+ end
+
+ HEADER2: begin
+ fifodata[`CHAN] <= 0;
+ fifodata[`RSSI] <= 0;
+ fifodata[`BURST] <= 0;
+ fifodata[`DROPPED] <= 0;
+ fifodata[`UNDERRUN] <= 0;
+ fifodata[`OVERRUN] <= 0;
+
+ state <= TIMESTAMP;
+ end
+
+ TIMESTAMP: begin
+ fifodata <= 0;
+ tstamp_complete <= ~tstamp_complete;
+
+ if (~tstamp_complete)
+ chan_rdreq[0] <= 1;
+
+ state <= (tstamp_complete ? FORWARD : TIMESTAMP);
+ end
+
+ FORWARD: begin
+ read_length <= read_length + 9'd2;
+ fifodata <= (read_length >= payload_len ? 16'hDEAD :
chan_fifodata);
+
+ if (read_length == `MAXPAYLOAD)
+ begin
+ WR <= 0;
+ state <= IDLE;
+ end
+ else if (read_length == payload_len - 4)
+ chan_rdreq <= 0;
+ end
+
+ default: begin
+ $display("error unknown state");
+ state <= IDLE;
+ end
+ endcase
+ end
+endmodule
+
Property changes on:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/packet_builder.v
___________________________________________________________________
Name: svn:executable
+ *
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-06-19 08:57:48 UTC (rev 5796)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-06-19 15:53:00 UTC (rev 5797)
@@ -1,7 +1,7 @@
//`include "../../firmware/include/fpga_regs_common.v"
//`include "../../firmware/include/fpga_regs_standard.v"
-module rx_buffer
+module rx_buffer_inband
( input usbclk,
input bus_reset,
input reset, // DSP side reset (used here), do not reset registers
@@ -42,8 +42,8 @@
read_count <= #1 RD ? read_count : 9'b0;
// USB side fifo
- wire [9:0] rdusedw;
- wire [9:0] wrusedw;
+ wire [8:0] rdusedw;
+ wire [8:0] wrusedw;
wire [15:0] fifodata;
wire WR;
wire have_space;
@@ -61,42 +61,62 @@
.wrfull ( ),
.wrusedw ( wrusedw ) );
- assign have_pkt_ready = (rdusedw >= 256);
+ assign have_pkt_rdy = (rdusedw >= 256);
assign have_space = (wrusedw < 256);
// Rx side fifos
wire [NUM_CHAN:0] chan_rdreq;
wire [15:0] chan_fifodata;
+ wire [9:0] chan_usedw;
wire [NUM_CHAN:0] chan_empty;
wire [NUM_CHAN:0] rd_select;
+ wire [NUM_CHAN:0] rx_full;
- packet_builer rx_pkt_builer (
+ packet_builder #(NUM_CHAN) rx_pkt_builer (
.rxclk ( rxclk ),
- .reset ( reset ),
-
+ .reset ( reset ),
.chan_rdreq ( chan_rdreq ),
.chan_fifodata ( chan_fifodata ),
.chan_empty ( chan_empty ),
-
- .rd_select(rd_select),
+ .rd_select ( rd_select ),
+ .chan_usedw ( chan_usedw ),
.WR ( WR ),
- .fifodata ( fifodata ) );
+ .fifodata ( fifodata ),
+ .have_space ( have_space ) );
+ // Detect overrun
+ always @(posedge rxclk)
+ if(reset)
+ rx_overrun <= 1'b0;
+ else if(rx_full[0] || rx_full[1])
+ rx_overrun <= 1'b1;
+ else if(clear_status)
+ rx_overrun <= 1'b0;
+
+ /* TODO write this genericly */
+ wire [15:0]ch[NUM_CHAN:0];
+ assign ch[0] = ch_0;
+ assign ch[1] = ch_1;
+
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_fifos
- wire [15:0] data;
- assign chan_fifodata = (rd_select[i] ? data : 16'bZ);
+ wire [15:0] dataout;
+ wire [9:0] usedw;
+
+ assign chan_fifodata = (rd_select[i] ? dataout : 16'bZ);
+ assign chan_usedw = (rd_select[i] ? usedw : 10'bZ);
+ assign chan_empty[i] = usedw < 10'd2;
fifo_2k_1clk rx_chan_fifo (
.aclr ( reset ),
.clock ( rxclk ),
- .data ( data ),
+ .data ( ch[i] ),
.rdreq ( chan_rdreq[i] ),
- .wrreq ( ),
- .empty ( chan_empty[i] ),
- .full ( ),
- .q ( ),
- .usedw ( ) );
+ .wrreq ( ~rx_full[i] & rxstrobe & (i==0)),
+ .empty ( ),
+ .full ( rx_full[i] ),
+ .q ( dataout ),
+ .usedw ( usedw ) );
end
endgenerate
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-06-19 08:57:48 UTC (rev 5796)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-06-19 15:53:00 UTC (rev 5797)
@@ -372,6 +372,9 @@
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition
-to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps"
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k_1clk.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/packet_builder.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/rx_buffer_inband.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v
set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1k.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_fifo_writer.v
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-06-19 08:57:48 UTC (rev 5796)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-06-19 15:53:00 UTC (rev 5797)
@@ -19,7 +19,8 @@
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
-`define IN_BAND
+`define TX_IN_BAND
+//`define RX_IN_BAND
`include "config.vh"
`include "../../../firmware/include/fpga_regs_common.v"
@@ -123,7 +124,7 @@
assign bb_tx_i1 = ch2tx;
assign bb_tx_q1 = ch3tx;
-`ifdef IN_BAND
+`ifdef TX_IN_BAND
tx_buffer_inband tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
@@ -235,7 +236,21 @@
.ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
.ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
.ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) );
-
+ `ifdef RX_IN_BAND
+ rx_buffer_inband rx_buffer
+ ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
+ .reset_regs(rx_dsp_reset),
+
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
+ .channels(rx_numchan),
+ .ch_0(ch0rx),.ch_1(ch1rx),
+ .ch_2(ch2rx),.ch_3(ch3rx),
+ .ch_4(ch4rx),.ch_5(ch5rx),
+ .ch_6(ch6rx),.ch_7(ch7rx),
+ .rxclk(clk64),.rxstrobe(hb_strobe),
+ .clear_status(clear_status),
+
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .debugbus(rx_debugbus) );
+ `else
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
@@ -249,6 +264,7 @@
.clear_status(clear_status),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.debugbus(rx_debugbus) );
+ `endif
`ifdef RX_EN_0
rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
Modified: gnuradio/branches/developers/thottelt/simulations/rx_fake_fx2.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/rx_fake_fx2.v
2007-06-19 08:57:48 UTC (rev 5796)
+++ gnuradio/branches/developers/thottelt/simulations/rx_fake_fx2.v
2007-06-19 15:53:00 UTC (rev 5797)
@@ -15,7 +15,8 @@
/* NOT USED YET */
reg clear_status;
-reg channels;
+reg [3:0]channels;
+reg SEN;
rx_buffer_inband rx_buffer_inband_ (
.usbclk(usbclk),
@@ -40,32 +41,42 @@
strobe_gen strobe_gen_test(
.clock(rxclk),
.reset(reset),
- .enable(1'd1),
- .rate(8'd6),
+ .enable(SEN),
+ .rate(8'd4),
.strobe_in(1'd1),
.strobe(rxstrobe) );
+
+rx_chains fake_rx_chains (
+ .rxclk(rxclk),
+ .reset(reset),
+ .rxstrobe(rxstrobe),
+ .ch_0(ch_0),
+ .ch_1(ch_1) );
initial begin
usbclk = 0;
rxclk = 0;
RD = 0;
+ SEN = 0;
reset = 1;
bus_reset = 1;
clear_status = 0;
channels = 0;
- #400 reset = 0;
+ #384 reset = 0;
bus_reset = 0;
+ #528 SEN = 1;
end
reg [3:0]state;
reg [8:0]count;
parameter IDLE = 0;
-parameter RCV = 1;
+parameter WAIT = 1;
+parameter RCV = 2;
-always @(posedge usbclk)
+always @(negedge usbclk)
begin
if (bus_reset)
state <= IDLE;
@@ -73,17 +84,20 @@
IDLE: begin
if (have_pkt_rdy)
begin
- state <= RCV;
- count <= 1;
+ state <= WAIT;
+ RD <= 1;
+ count <= 0;
end
end
+ WAIT: state <= RCV;
+
RCV: begin
count <= count + 1;
- RD <= 1;
- $display(usbdata);
+ if (usbdata != 16'hDEAD)
+ $display(usbdata);
- if (count == 257)
+ if (count == 256)
begin
RD <= 0;
state <= IDLE;
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-19
08:57:48 UTC (rev 5796)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-19
15:53:00 UTC (rev 5797)
@@ -131,7 +131,7 @@
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
-resolution = 1ns
+resolution = 1ps
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
@@ -140,7 +140,7 @@
UserTimeUnit = default
; Default run length
-RunLength = 0 ns
+RunLength = 0 ps
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
@@ -243,29 +243,29 @@
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
-Project_Files_Count = 26
+Project_Files_Count = 28
Project_File_0 = ./strobe_gen_test.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177269906 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = ./usb_fifo_writer_test.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
14 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_2 = ../inband/usrp/fpga/inband_lib/channel_ram.v
+Project_File_2 = Z:/wc/inband/usrp/fpga/inband_lib/channel_ram.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575398 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = Z:/wc/simulations/data_packet_fifo_test.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_4 = ./fake_tx_chain.v
+Project_File_4 = Z:/wc/simulations/fake_tx_chain.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_5 = ../inband/usrp/fpga/megacells/fifo_2k.v
+Project_File_5 = Z:/wc/inband/usrp/fpga/megacells/fifo_2k.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
18 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_6 = ../inband/usrp/fpga/sdr_lib/tx_chain.v
+Project_File_6 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_chain.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
20 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_7 = ./fake_fx2_test.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177428969 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_8 = ./fake_fx2.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575379 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
11 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_9 = ../inband/usrp/fpga/inband_lib/packet_builder.v
-Project_File_P_9 = vlog_protect 0 cover_toggle 0 vhdl_novitalcheck 0
cover_exttoggle 0 file_type verilog group_id 0 vhdl_nodebug 0 vhdl_1164 1
cover_cond 0 vhdl_noload 0 vlog_nodebug 0 vlog_1995compat 0 vhdl_enable0In 0
vhdl_synth 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile
1181669605 vhdl_disableopt 0 vlog_enable0In 0 vhdl_vital 0 vlog_disableopt 0
vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0
vlog_vopt 0 vlog_optionfile Z:/wc/simulations/vlog.opt vhdl_warn3 1
vhdl_0InOptions {} vlog_showsource 0 vlog_hazard 0 vhdl_warn4 1 vhdl_options {}
vlog_0InOptions {} vhdl_warn5 1 ood 0 vlog_options {} vlog_upper 0 compile_to
work compile_order 24 cover_expr 0 cover_nosub 0 dont_compile 0 cover_stmt 0
vhdl_use93 2002
-Project_File_10 = ../inband/usrp/fpga/inband_lib/rx_buffer_inband.v
-Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181667372 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 23
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_9 = Z:/wc/inband/usrp/fpga/inband_lib/packet_builder.v
+Project_File_P_9 = vlog_protect 0 cover_toggle 0 vhdl_novitalcheck 0
cover_exttoggle 0 file_type verilog group_id 0 vhdl_nodebug 0 vhdl_1164 1
cover_cond 0 vhdl_noload 0 vlog_1995compat 0 vlog_nodebug 0 vhdl_synth 0
vhdl_enable0In 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile
1181926751 vhdl_disableopt 0 vlog_enable0In 0 vhdl_vital 0 vlog_disableopt 0
vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0
vlog_vopt 0 vlog_optionfile Z:/wc/simulations/vlog.opt vhdl_warn3 1
vhdl_0InOptions {} vlog_showsource 0 vlog_hazard 0 vhdl_warn4 1 vhdl_options {}
vlog_0InOptions {} vhdl_warn5 1 ood 0 vlog_options {} vlog_upper 0 compile_to
work compile_order 24 cover_expr 0 cover_nosub 0 dont_compile 0 cover_stmt 0
vhdl_use93 2002
+Project_File_10 = Z:/wc/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1182198467 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 23
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_11 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575461 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_12 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
@@ -280,7 +280,7 @@
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181590269 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_17 = ./usb_packet_fifo_test.v
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177365360 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_18 = ../inband/usrp/fpga/sdr_lib/tx_buffer.v
+Project_File_18 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
19 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_19 = ./tx_buffer_test.v
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179008242 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3
dont_compile 0 cover_expr 0 cover_stmt 0
@@ -288,14 +288,18 @@
Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575398 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_21 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_22 = ./rx_fake_fx2.v
-Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181673958 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 25
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_23 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
-Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_24 = ./channel_ram_test.v
-Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_25 = ./usb_fifo_reader_test.v
-Project_File_P_25 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178397904 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_22 = Z:/wc/simulations/rx_chains.v
+Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181852410 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 26
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_23 = Z:/wc/simulations/rx_fake_fx2.v
+Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181863921 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
25 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_24 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
+Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_25 = Z:/wc/simulations/channel_ram_test.v
+Project_File_P_25 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_26 = Z:/wc/inband/usrp/fpga/megacells/fifo_2k_1clk.v
+Project_File_P_26 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181850595 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
27 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_27 = ./usb_fifo_reader_test.v
+Project_File_P_27 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178397904 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
@@ -325,6 +329,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1} {Z:/wc/simulations/rx_fake_fx2.v 0 1}
{Z:/wc/inband/usrp/fpga/inband_lib/rx_buffer_inband.v 0 0}
+EditorState = {tabbed horizontal 1}
{Z:/wc/inband/usrp/fpga/inband_lib/rx_buffer_inband.v 0 1}
{Z:/wc/inband/usrp/fpga/inband_lib/packet_builder.v 0 0}
{Z:/wc/simulations/rx_fake_fx2.v 0 0}
Project_Major_Version = 6
Project_Minor_Version = 1
Modified: gnuradio/branches/developers/thottelt/simulations/work/_info
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/work/_info
2007-06-19 08:57:48 UTC (rev 5796)
+++ gnuradio/branches/developers/thottelt/simulations/work/_info
2007-06-19 15:53:00 UTC (rev 5797)
@@ -628,6 +628,19 @@
31
o-work work -O0
tGenerateLoopIterationMax 100000
+vfifo_2k_1clk
+IeYoBZ14E0:address@hidden
+VC:bUKg`=_Gz9UcZ=6<Uj<0
+dZ:\wc\simulations
+w1181850595
+FZ:/wc/inband/usrp/fpga/megacells/fifo_2k_1clk.v
+L0 36
+VC:bUKg`=_Gz9UcZ=6<Uj<0
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
vfifo_2k_a_gray2bin_8m4
I>@_N>R6:]>bNj=gmP:iSb1
address@hidden;S0
@@ -1088,13 +1101,13 @@
tGenerateLoopIterationMax 100000
address@hidden@f_stratixii_pll
vpacket_builder
-I2253D8l_MP[;>7iknkd`F1
-V2mmbTUOM4W=7m_fz;QX_O1
+IN6la^ACW]oE[MW<H?M1dO2
+VKa]1?4R;5jIeg<_:nF7Ya3
dZ:\wc\simulations
-w1181669605
+w1181926751
FZ:/wc/inband/usrp/fpga/inband_lib/packet_builder.v
L0 1
-V2mmbTUOM4W=7m_fz;QX_O1
+VKa]1?4R;5jIeg<_:nF7Ya3
OV;L;6.1g;31
r1
31
@@ -1126,14 +1139,40 @@
31
o-work work -O0
tGenerateLoopIterationMax 100000
+vrx_buffer_inband
+IbL<:8Rea0<Aj`=8_S8hZ=0
+V>address@hidden
+dZ:\wc\simulations
+w1182198467
+FZ:/wc/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
+L0 4
+V>address@hidden
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
+vrx_chains
+I<6?=[iCFLB6jU<3b[aHn?1
address@hidden
+dZ:\wc\simulations
+w1181852410
+FZ:/wc/simulations/rx_chains.v
+L0 1
address@hidden
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
vrx_fake_fx2
-I4<F12]X1kfILZ3S[aReZH1
-VL2FzV[S<I?j340Y^RP48o2
+I[SMU<dW[c4PojT7AWHc643
+V<Zz<:address@hidden:=9n>O:i3
dZ:\wc\simulations
-w1181673958
+w1181863921
FZ:/wc/simulations/rx_fake_fx2.v
L0 1
-VL2FzV[S<I?j340Y^RP48o2
+V<Zz<:address@hidden:=9n>O:i3
OV;L;6.1g;31
r1
31
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- [Commit-gnuradio] r5797 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/toplevel/usrp_inband_usb simulations simulations/work,
thottelt <=