[Commit-gnuradio] r5821 - gnuradio/branches/developers/matt/u2f/top/u2_fpga

[matt]

Author: matt
Date: 2007-06-23 18:39:35 -0600 (Sat, 23 Jun 2007)
New Revision: 5821

Added:
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj
Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
Log:
not sure if we need this new file


Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
===================================================================
(Binary files differ)

Added: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj           
                (rev 0)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj   
2007-06-24 00:39:35 UTC (rev 5821)
@@ -0,0 +1,41 @@
+verilog work "../../sdr_lib/sign_extend.v"
+verilog work "../../sdr_lib/cordic_stage.v"
+verilog work "../../sdr_lib/cic_int_shifter.v"
+verilog work "../../sdr_lib/cic_dec_shifter.v"
+verilog work "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_regfile.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_fetch.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_decode.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_control.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_aslu.v"
+verilog work "../../sdr_lib/cordic.v"
+verilog work "../../sdr_lib/cic_interp.v"
+verilog work "../../sdr_lib/cic_decim.v"
+verilog work "../../opencores/spi/rtl/verilog/spi_shift.v"
+verilog work "../../opencores/spi/rtl/verilog/spi_clgen.v"
+verilog work "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_core.v"
+verilog work "../../control_lib/strobe_gen.v"
+verilog work "../../control_lib/shortfifo.v"
+verilog work "../../control_lib/setting_reg.v"
+verilog work "../../control_lib/fifo_int.v"
+verilog work "../../control_lib/decoder_3_8.v"
+verilog work "../../control_lib/buffer_2k.v"
+verilog work "../../control_lib/CRC16_D16.v"
+verilog work "../../sdr_lib/dsp_core_tx.v"
+verilog work "../../sdr_lib/dsp_core_rx.v"
+verilog work "../../opencores/spi/rtl/verilog/spi_top.v"
+verilog work "../../opencores/simple_gpio/rtl/simple_gpio.v"
+verilog work "../../opencores/i2c/rtl/verilog/i2c_master_top.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v"
+verilog work "../../control_lib/wb_output_pins32.v"
+verilog work "../../control_lib/wb_1master.v"
+verilog work "../../control_lib/system_control.v"
+verilog work "../../control_lib/settings_bus.v"
+verilog work "../../control_lib/serdes_tx.v"
+verilog work "../../control_lib/serdes_rx.v"
+verilog work "../../control_lib/ram_wb_harvard.v"
+verilog work "../../control_lib/ram_loader.v"
+verilog work "../../control_lib/buffer_pool.v"
+verilog work "../u2_basic/u2_basic.v"
+verilog work "u2_fpga_top.v"