[Commit-gnuradio] r5828 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-06-25 12:36:26 -0600 (Mon, 25 Jun 2007)
New Revision: 5828

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
Log:
added in all the new ports for error and clear


Modified: gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v     
2007-06-24 20:57:00 UTC (rev 5827)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v     
2007-06-25 18:36:26 UTC (rev 5828)
@@ -29,16 +29,16 @@
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
    
    // Write Interfaces
-   input [31:0] wr0_dat_i, input wr0_write_i, input wr0_done_i, output 
wr0_ready_o, output wr0_full_o,
-   input [31:0] wr1_dat_i, input wr1_write_i, input wr1_done_i, output 
wr1_ready_o, output wr1_full_o,
-   input [31:0] wr2_dat_i, input wr2_write_i, input wr2_done_i, output 
wr2_ready_o, output wr2_full_o,
-   input [31:0] wr3_dat_i, input wr3_write_i, input wr3_done_i, output 
wr3_ready_o, output wr3_full_o,
+   input [31:0] wr0_dat_i, input wr0_write_i, input wr0_done_i, input 
wr0_error_i, output wr0_ready_o, output wr0_full_o,
+   input [31:0] wr1_dat_i, input wr1_write_i, input wr1_done_i, input 
wr1_error_i, output wr1_ready_o, output wr1_full_o,
+   input [31:0] wr2_dat_i, input wr2_write_i, input wr2_done_i, input 
wr2_error_i, output wr2_ready_o, output wr2_full_o,
+   input [31:0] wr3_dat_i, input wr3_write_i, input wr3_done_i, input 
wr3_error_i, output wr3_ready_o, output wr3_full_o,
    
    // Read Interfaces
-   output [31:0] rd0_dat_o, input rd0_read_i, input rd0_done_i, output 
rd0_ready_o, output rd0_empty_o,
-   output [31:0] rd1_dat_o, input rd1_read_i, input rd1_done_i, output 
rd1_ready_o, output rd1_empty_o,
-   output [31:0] rd2_dat_o, input rd2_read_i, input rd2_done_i, output 
rd2_ready_o, output rd2_empty_o,
-   output [31:0] rd3_dat_o, input rd3_read_i, input rd3_done_i, output 
rd3_ready_o, output rd3_empty_o
+   output [31:0] rd0_dat_o, input rd0_read_i, input rd0_done_i, input 
rd0_error_i, output rd0_ready_o, output rd0_empty_o,
+   output [31:0] rd1_dat_o, input rd1_read_i, input rd1_done_i, input 
rd1_error_i, output rd1_ready_o, output rd1_empty_o,
+   output [31:0] rd2_dat_o, input rd2_read_i, input rd2_done_i, input 
rd2_error_i, output rd2_ready_o, output rd2_empty_o,
+   output [31:0] rd3_dat_o, input rd3_read_i, input rd3_done_i, input 
rd3_error_i, output rd3_ready_o, output rd3_empty_o
    );
 
    wire [7:0] sel_a;
@@ -57,7 +57,11 @@
    wire        write_go[0:7];
    wire [1:0]  read_port[0:7];
    wire [1:0]  write_port[0:7];
-   wire [3:0]  dummy[0:7];
+   wire [2:0]  dummy[0:7];
+   wire        clear [0:7];       
+   wire        done[0:7];
+   wire        error[0:7];
+
    wire        changed [0:7];
 
    wire [31:0] buf_doa[0:7];
@@ -68,34 +72,36 @@
    wire [31:0] buf_dib[0:7];
    wire [31:0] buf_dob[0:7];
    
-   wire        done[0:7];
-
    wire [31:0] wr_dat_i[0:7];
    wire        wr_write_i[0:7];
    wire        wr_done_i[0:7];
+   wire        wr_error_i[0:7];
    wire        wr_ready_o[0:7];
    wire        wr_full_o[0:7];
 
    wire [31:0] rd_dat_o[0:7];
    wire        rd_read_i[0:7];
    wire        rd_done_i[0:7];
+   wire        rd_error_i[0:7];
    wire        rd_ready_o[0:7];
    wire        rd_empty_o[0:7];
    
+   wire [15:0] status = {error[7:0],done[7:0]};
    
    generate
       for(i=0;i<8;i=i+1)
        begin : gen_buffer
           setting_reg #(.my_addr(i)) 
             
sreg(.clk(stream_clk),.rst(stream_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),
-                 
.out({dummy[i],read_port[i],write_port[i],write_go[i],read_go[i],step[i],ll[i],fl[i]}),.changed(changed[i]));
+                 
.out({dummy[i],clear[i],read_port[i],write_port[i],write_go[i],read_go[i],step[i],ll[i],fl[i]}),.changed(changed[i]));
           ram_2port #(.DWIDTH(32),.AWIDTH(9)) buffer
             (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[i]),.wea(wb_we_i),
              .addra(buf_addra),.dia(wb_dat_i),.doa(buf_doa[i]),
              
.clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]),.addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i]));
 
           fifo_int fifo_int
             
(.clk(stream_clk),.rst(stream_rst),.firstline(fl[i]),.lastline(ll[i]),
-             
.step(step[i]),.read_go(changed[i]&read_go[i]),.write_go(changed[i]&write_go[i]),.done(done[i]),
+             
.step(step[i]),.read_go(changed[i]&read_go[i]),.write_go(changed[i]&write_go[i]),
+             .clear(changed[i]&clear[i]),.done(done[i]),.error(error[i]),
              .en_o(buf_enb[i]),
              .we_o(buf_web[i]),
              .addr_o(buf_addrb[i]),
@@ -104,11 +110,13 @@
              .wr_dat_i(wr_dat_i[i]),
              .wr_write_i(wr_write_i[i]),
              .wr_done_i(wr_done_i[i]),
+             .wr_error_i(wr_error_i[i]),
              .wr_ready_o(wr_ready_o[i]),
              .wr_full_o(wr_full_o[i]),
              .rd_dat_o(rd_dat_o[i]),
              .rd_read_i(rd_read_i[i]),
              .rd_done_i(rd_done_i[i]),
+             .rd_error_i(rd_error_i[i]),
              .rd_ready_o(rd_ready_o[i]),
              .rd_empty_o(rd_empty_o[i]) 
              );
@@ -122,11 +130,17 @@
             mux4_wrdone_i (.sel(write_port[i]),.i0(wr0_done_i),.i1(wr1_done_i),
                            .i2(wr2_done_i),.i3(wr3_done_i),.o(wr_done_i[i]));
           mux4 #(.WIDTH(1)) 
+            mux4_wrerror_i 
(.sel(write_port[i]),.i0(wr0_error_i),.i1(wr1_error_i),
+                            
.i2(wr2_error_i),.i3(wr3_error_i),.o(wr_error_i[i]));
+          mux4 #(.WIDTH(1)) 
+            mux4_read_i (.sel(read_port[i]),.i0(rd0_read_i),.i1(rd1_read_i),
+                         .i2(rd2_read_i),.i3(rd3_read_i),.o(rd_read_i[i]));
+          mux4 #(.WIDTH(1)) 
             mux4_rddone_i (.sel(read_port[i]),.i0(rd0_done_i),.i1(rd1_done_i),
                            .i2(rd2_done_i),.i3(rd3_done_i),.o(rd_done_i[i]));
           mux4 #(.WIDTH(1)) 
-            mux4_read_i (.sel(read_port[i]),.i0(rd0_read_i),.i1(rd1_read_i),
-                         .i2(rd2_read_i),.i3(rd3_read_i),.o(rd_read_i[i]));
+            mux4_rderror_i 
(.sel(read_port[i]),.i0(rd0_error_i),.i1(rd1_error_i),
+                            
.i2(rd2_error_i),.i3(rd3_error_i),.o(rd_error_i[i]));
        end // block: gen_buffer
    endgenerate