[Commit-gnuradio] r5840 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-06-25 20:53:59 -0600 (Mon, 25 Jun 2007)
New Revision: 5840

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
Log:
new states and lines for error and clear


Modified: gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v        
2007-06-26 02:50:20 UTC (rev 5839)
+++ gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v        
2007-06-26 02:53:59 UTC (rev 5840)
@@ -11,7 +11,9 @@
    input [3:0] step,
    input read_go,
    input write_go,
+   input clear,
    output done,
+   output error,
    
    // Buffer Interface
    output en_o,
@@ -24,6 +26,7 @@
    input [31:0] wr_dat_i,
    input wr_write_i,
    input wr_done_i,
+   input wr_error_i,
    output wr_ready_o,
    output wr_full_o,
    
@@ -31,6 +34,7 @@
    output [31:0] rd_dat_o,
    input rd_read_i,
    input rd_done_i,
+   input rd_error_i,
    output rd_ready_o,
    output rd_empty_o
    );
@@ -48,6 +52,7 @@
    localparam PRE_READ = 3'd1;
    localparam READING = 3'd2;
    localparam WRITING = 3'd3;
+   localparam ERROR = 3'd4;
 
    reg [3:0]  state;
    
@@ -57,57 +62,69 @@
          addr_o <= 0;
          state <= IDLE;
        end
-     else 
-       case(state)
-        IDLE :
-          if(read_go)
+     else
+       if(clear)
+        state <= IDLE;
+       else 
+        case(state)
+          IDLE :
+            if(read_go)
+              begin
+                 addr_o <= firstline;
+                 state <= PRE_READ;
+              end
+            else if(write_go)
+              begin
+                 addr_o <= firstline;
+                 state <= WRITING;
+              end
+          
+          PRE_READ :
             begin
-               addr_o <= firstline;
-               state <= PRE_READ;
+               state <= READING;
+               addr_o <= addr_o + 1;
             end
-          else if(write_go)
+          
+          READING :
+            if(rd_read_i)
+              begin
+                 addr_o <= addr_o + 1;
+                 if(rd_error_i)
+                   state <= ERROR;
+                 else if(addr_o == lastline + 9'd1)
+                   state <= IDLE;
+              end
+          
+          WRITING :
             begin
-               addr_o <= firstline;
-               state <= WRITING;
-            end
-        
-        PRE_READ :
-          begin
-             state <= READING;
-             addr_o <= addr_o + 1;
-          end
-
-        READING :
-          if(rd_read_i)
-            begin
-               addr_o <= addr_o + 1;
-               if(addr_o == lastline + 9'd1)
-                 state <= IDLE;
-            end
-
-        WRITING :
-          begin
-             if(wr_write_i)
-               begin
-                  addr_o <= addr_o + 1;
-                  if(addr_o == lastline)
-                    state <= IDLE;
-               end
-             if(wr_done_i)
-               state <= IDLE;
-          end
-
-       endcase // case(state)
-
+               if(wr_error_i)
+                 state <= ERROR;
+               else
+                 begin
+                    if(wr_write_i)
+                      begin
+                         addr_o <= addr_o + 1;
+                         if(addr_o == lastline)
+                           state <= IDLE;
+                      end
+                    if(wr_done_i)
+                      state <= IDLE;
+                 end // else: !if(wr_error_i)
+            end // case: WRITING
+          
+        endcase // case(state)
+   
    // FIXME read side ignores rd_done_i for now
    
    assign rd_en = (state == PRE_READ) || ((state == READING) && rd_read_i);
    assign rd_empty_o = (state != READING) && (state != PRE_READ);
    assign rd_ready_o = (state == READING);
-
+   
    assign wr_en = (state == WRITING) && wr_write_i;  // IF this is a timing 
problem, we could always enable when in this state
    assign we_o = (state == WRITING) && wr_write_i;  // IF this is a timing 
problem, we could always write when in this state
    assign wr_full_o = (state != WRITING);
    assign wr_ready_o = (state == WRITING);
-   
+
+   assign done = (state == IDLE);
+   assign error = (state == ERROR);
 endmodule // fifo_int