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[Commit-gnuradio] r5846 - in gnuradio/branches/developers/thottelt: inba
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From: |
thottelt |
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Subject: |
[Commit-gnuradio] r5846 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/toplevel/usrp_inband_usb inband/usrp/host/lib/inband simulations simulations/work |
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Date: |
Tue, 26 Jun 2007 15:42:31 -0600 (MDT) |
Author: thottelt
Date: 2007-06-26 15:42:30 -0600 (Tue, 26 Jun 2007)
New Revision: 5846
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/packet_builder.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
gnuradio/branches/developers/thottelt/inband/usrp/host/lib/inband/gen_test_packets.py
gnuradio/branches/developers/thottelt/simulations/all_valid_packet_lengths_1_channel.dat
gnuradio/branches/developers/thottelt/simulations/all_valid_packet_lengths_2_channels.dat
gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
gnuradio/branches/developers/thottelt/simulations/rx_fake_fx2.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
gnuradio/branches/developers/thottelt/simulations/work/_info
Log:
Command handling infrastructure done
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/packet_builder.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/packet_builder.v
2007-06-26 19:30:56 UTC (rev 5845)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/packet_builder.v
2007-06-26 21:42:30 UTC (rev 5846)
@@ -1,114 +1,121 @@
-module packet_builder #(parameter NUM_CHAN = 2) (
- // System
- input rxclk,
- input reset,
- input [31:0] adctime,
- // ADC side
- input [15:0]chan_fifodata,
- input [NUM_CHAN:0]chan_empty,
- input [9:0]chan_usedw,
- output reg [NUM_CHAN:0]rd_select,
- output reg [NUM_CHAN:0]chan_rdreq,
- // FX2 side
- output reg WR,
- output reg [15:0]fifodata,
- input have_space );
-
- parameter IDLE = 0;
- parameter HEADER1 = 1;
- parameter HEADER2 = 2;
- parameter TIMESTAMP = 3;
- parameter FORWARD = 4;
-
- `define MAXPAYLOAD 504
-
- `define PAYLOAD_LEN 8:0
- `define TAG 12:9
- `define MBZ 15:13
-
- `define CHAN 4:0
- `define RSSI 10:5
- `define BURST 12:11
- `define DROPPED 13
- `define UNDERRUN 14
- `define OVERRUN 15
-
- reg [3:0] state;
- reg [8:0] read_length;
- reg [8:0] payload_len;
- reg tstamp_complete;
-
- always @(posedge rxclk)
- begin
- if (reset)
- begin
- WR <= 0;
- rd_select[0] <= 1;
- rd_select[1] <= 0;
- rd_select[2] <= 0;
- chan_rdreq <= 0;
- tstamp_complete <= 0;
- state <= IDLE;
- end
- else case (state)
- IDLE: begin
-
- if (~chan_empty[0] && have_space)
- state <= #1 HEADER1;
- end
-
- HEADER1: begin
- fifodata[`PAYLOAD_LEN] <= #1 (chan_usedw > 9'd252
- ? 9'd252 : chan_usedw << 1);
- payload_len <= #1 (chan_usedw > 9'd252
- ? 9'd252 : chan_usedw << 1);
- fifodata[`TAG] <= #1 0;
- fifodata[`MBZ] <= #1 0;
- WR <= #1 1;
-
- state <= #1 HEADER2;
- read_length <= #1 0;
- end
-
- HEADER2: begin
- fifodata[`CHAN] <= #1 0;
- fifodata[`RSSI] <= #1 0;
- fifodata[`BURST] <= #1 0;
- fifodata[`DROPPED] <= #1 0;
- fifodata[`UNDERRUN] <= #1 0;
- fifodata[`OVERRUN] <= #1 0;
-
- state <= #1 TIMESTAMP;
- end
-
- TIMESTAMP: begin
- fifodata <= #1 (tstamp_complete ? adctime[31:16] :
adctime[15:0]);
- tstamp_complete <= #1 ~tstamp_complete;
-
- if (~tstamp_complete)
- chan_rdreq[0] <= #1 1;
-
- state <= #1 (tstamp_complete ? FORWARD : TIMESTAMP);
- end
-
- FORWARD: begin
- read_length <= #1 read_length + 9'd2;
- fifodata <= #1 (read_length >= payload_len ? 16'hDEAD :
chan_fifodata);
-
- if (read_length >= `MAXPAYLOAD)
- begin
- WR <= #1 0;
- state <= #1 IDLE;
- end
- else if (read_length == payload_len - 4)
- chan_rdreq <= #1 0;
- end
-
- default: begin
- $display("error unknown state");
- state <= IDLE;
- end
- endcase
- end
-endmodule
-
+module packet_builder #(parameter NUM_CHAN = 1) (
+ // System
+ input rxclk,
+ input reset,
+ input [31:0] adctime,
+ input [3:0] channels,
+ // ADC side
+ input [15:0]chan_fifodata,
+ input [NUM_CHAN:0]chan_empty,
+ input [9:0]chan_usedw,
+ output reg [3:0]rd_select,
+ output reg chan_rdreq,
+ // FX2 side
+ output reg WR,
+ output reg [15:0]fifodata,
+ input have_space );
+
+ parameter IDLE = 0;
+ parameter HEADER1 = 1;
+ parameter HEADER2 = 2;
+ parameter TIMESTAMP = 3;
+ parameter FORWARD = 4;
+
+ `define MAXPAYLOAD 504
+
+ `define PAYLOAD_LEN 8:0
+ `define TAG 12:9
+ `define MBZ 15:13
+
+ `define CHAN 4:0
+ `define RSSI 10:5
+ `define BURST 12:11
+ `define DROPPED 13
+ `define UNDERRUN 14
+ `define OVERRUN 15
+
+ reg [3:0] state;
+ reg [8:0] read_length;
+ reg [8:0] payload_len;
+ reg tstamp_complete;
+ reg [3:0] check_next;
+
+ always @(posedge rxclk)
+ begin
+ if (reset)
+ begin
+ WR <= 0;
+ rd_select <= 0;
+ chan_rdreq <= 0;
+ tstamp_complete <= 0;
+ check_next <= 0;
+ state <= IDLE;
+ end
+ else case (state)
+ IDLE: begin
+ if (have_space)
+ begin
+ if(~chan_empty[check_next])
+ begin
+ state <= #1 HEADER1;
+ rd_select <= #1 check_next;
+ end
+ check_next <= #1 (check_next ==
channels ? 4'd0 : check_next + 4'd1);
+ end
+ end
+
+ HEADER1: begin
+ fifodata[`PAYLOAD_LEN] <= #1 (chan_usedw > 9'd252
+ ? 9'd252 : chan_usedw << 1);
+ payload_len <= #1 (chan_usedw > 9'd252
+ ? 9'd252 : chan_usedw << 1);
+ fifodata[`TAG] <= #1 0;
+ fifodata[`MBZ] <= #1 0;
+ WR <= #1 1;
+
+ state <= #1 HEADER2;
+ read_length <= #1 0;
+ end
+
+ HEADER2: begin
+ fifodata[`CHAN] <= #1 (check_next == 4'd0 ? 5'h1f : {1'd0,
check_next - 4'd1});
+ fifodata[`RSSI] <= #1 0;
+ fifodata[`BURST] <= #1 0;
+ fifodata[`DROPPED] <= #1 0;
+ fifodata[`UNDERRUN] <= #1 0;
+ fifodata[`OVERRUN] <= #1 0;
+
+ state <= #1 TIMESTAMP;
+ end
+
+ TIMESTAMP: begin
+ fifodata <= #1 (tstamp_complete ? adctime[31:16] :
adctime[15:0]);
+ tstamp_complete <= #1 ~tstamp_complete;
+
+ if (~tstamp_complete)
+ chan_rdreq <= #1 1;
+
+ state <= #1 (tstamp_complete ? FORWARD : TIMESTAMP);
+ end
+
+ FORWARD: begin
+ read_length <= #1 read_length + 9'd2;
+ fifodata <= #1 (read_length >= payload_len ? 16'hDEAD :
chan_fifodata);
+
+ if (read_length >= `MAXPAYLOAD)
+ begin
+ WR <= #1 0;
+ state <= #1 IDLE;
+ end
+ else if (read_length == payload_len - 4)
+ chan_rdreq <= #1 0;
+ end
+
+ default: begin
+ $display("error unknown state");
+ state <= IDLE;
+ end
+ endcase
+ end
+endmodule
+
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-06-26 19:30:56 UTC (rev 5845)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-06-26 21:42:30 UTC (rev 5846)
@@ -1,140 +1,147 @@
-//`include "../../firmware/include/fpga_regs_common.v"
-//`include "../../firmware/include/fpga_regs_standard.v"
-
-module rx_buffer_inband
- ( input usbclk,
- input bus_reset,
- input reset, // DSP side reset (used here), do not reset registers
- input reset_regs, //Only reset registers
- output [15:0] usbdata,
- input RD,
- output wire have_pkt_rdy,
- output reg rx_overrun,
- input wire [3:0] channels,
- input wire [15:0] ch_0,
- input wire [15:0] ch_1,
- input wire [15:0] ch_2,
- input wire [15:0] ch_3,
- input wire [15:0] ch_4,
- input wire [15:0] ch_5,
- input wire [15:0] ch_6,
- input wire [15:0] ch_7,
- input rxclk,
- input rxstrobe,
- input clear_status,
- input [6:0] serial_addr,
- input [31:0] serial_data,
- input serial_strobe,
- output [15:0] debugbus
- );
-
- parameter NUM_CHAN = 2;
- genvar i ;
-
- // FX2 Bug Fix
- reg [8:0] read_count;
- always @(negedge usbclk)
- if(bus_reset)
- read_count <= #1 9'd0;
- else if(RD & ~read_count[8])
- read_count <= #1 read_count + 9'd1;
- else
- read_count <= #1 RD ? read_count : 9'b0;
-
- // Time counter
- reg [31:0] adctime;
- always @(posedge rxclk)
- if (reset)
- adctime <= 0;
- else if (rxstrobe)
- adctime <= adctime + 1;
-
- // USB side fifo
- wire [8:0] rdusedw;
- wire [8:0] wrusedw;
- wire [15:0] fifodata;
- wire WR;
- wire have_space;
-
- fifo_4k rx_usb_fifo (
- .aclr ( reset ),
- .data ( fifodata ),
- .rdclk ( ~usbclk ),
- .rdreq ( RD & ~read_count[8] ),
- .wrclk ( rxclk ),
- .wrreq ( WR ),
- .q ( usbdata ),
- .rdempty ( ),
- .rdusedw ( rdusedw ),
- .wrfull ( ),
- .wrusedw ( wrusedw ) );
-
- assign have_pkt_rdy = (rdusedw >= 256);
- assign have_space = (wrusedw < 760);
-
- // Rx side fifos
- wire [NUM_CHAN:0] chan_rdreq;
- wire [15:0] chan_fifodata;
- wire [9:0] chan_usedw;
- wire [NUM_CHAN:0] chan_empty;
- wire [NUM_CHAN:0] rd_select;
- wire [NUM_CHAN:0] rx_full;
-
- packet_builder #(NUM_CHAN) rx_pkt_builer (
- .rxclk ( rxclk ),
- .reset ( reset ),
- .adctime ( adctime ),
- .chan_rdreq ( chan_rdreq ),
- .chan_fifodata ( chan_fifodata ),
- .chan_empty ( chan_empty ),
- .rd_select ( rd_select ),
- .chan_usedw ( chan_usedw ),
- .WR ( WR ),
- .fifodata ( fifodata ),
- .have_space ( have_space ) );
-
- // Detect overrun
- always @(posedge rxclk)
- if(reset)
- rx_overrun <= 1'b0;
- else if(rx_full[0])
- rx_overrun <= 1'b1;
- else if(clear_status)
- rx_overrun <= 1'b0;
-
- reg [15:0] test;
- always @(posedge rxclk)
- if (reset)
- test <= 0;
- else if (~rx_full[0])
- test <= test + 1;
-
- // TODO write this genericly
- wire [15:0]ch[NUM_CHAN:0];
- assign ch[0] = ch_0;
- assign ch[1] = ch_1;
-
- generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
- begin : generate_channel_fifos
- wire [15:0] dataout;
- wire [9:0] usedw;
-
- assign chan_fifodata = (rd_select[i] ? dataout : 16'bZ);
- assign chan_usedw = (rd_select[i] ? usedw : 10'bZ);
- assign chan_empty[i] = usedw < 10'd126;
-
- fifo_2k_1clk rx_chan_fifo (
- .aclr ( reset ),
- .clock ( rxclk ),
- .data ( ch[i] ),
- .rdreq ( chan_rdreq[i] ),
- .wrreq ( ~rx_full[i] & rxstrobe ),
- .empty ( ),
- .full ( rx_full[i] ),
- .q ( dataout ),
- .usedw ( usedw ) );
- end
- endgenerate
-
- assign debugbus = 0;
-endmodule
+//`include "../../firmware/include/fpga_regs_common.v"
+//`include "../../firmware/include/fpga_regs_standard.v"
+
+module rx_buffer_inband
+ ( input usbclk,
+ input bus_reset,
+ input reset, // DSP side reset (used here), do not reset registers
+ input reset_regs, //Only reset registers
+ output [15:0] usbdata,
+ input RD,
+ output wire have_pkt_rdy,
+ output reg rx_overrun,
+ input wire [3:0] channels,
+ input wire [15:0] ch_0,
+ input wire [15:0] ch_1,
+ input wire [15:0] ch_2,
+ input wire [15:0] ch_3,
+ input wire [15:0] ch_4,
+ input wire [15:0] ch_5,
+ input wire [15:0] ch_6,
+ input wire [15:0] ch_7,
+ input rxclk,
+ input rxstrobe,
+ input clear_status,
+ input [6:0] serial_addr,
+ input [31:0] serial_data,
+ input serial_strobe,
+ output [15:0] debugbus,
+
+ //Connection with tx_inband
+ input rx_WR,
+ input [15:0] rx_databus
+ );
+
+ parameter NUM_CHAN = 1;
+ genvar i ;
+
+ // FX2 Bug Fix
+ reg [8:0] read_count;
+ always @(negedge usbclk)
+ if(bus_reset)
+ read_count <= #1 9'd0;
+ else if(RD & ~read_count[8])
+ read_count <= #1 read_count + 9'd1;
+ else
+ read_count <= #1 RD ? read_count : 9'b0;
+
+ // Time counter
+ reg [31:0] adctime;
+ always @(posedge rxclk)
+ if (reset)
+ adctime <= 0;
+ else if (rxstrobe)
+ adctime <= adctime + 1;
+
+ // USB side fifo
+ wire [11:0] rdusedw;
+ wire [11:0] wrusedw;
+ wire [15:0] fifodata;
+ wire WR;
+ wire have_space;
+
+ fifo_4k rx_usb_fifo (
+ .aclr ( reset ),
+ .data ( fifodata ),
+ .rdclk ( ~usbclk ),
+ .rdreq ( RD & ~read_count[8] ),
+ .wrclk ( rxclk ),
+ .wrreq ( WR ),
+ .q ( usbdata ),
+ .rdempty ( ),
+ .rdusedw ( rdusedw ),
+ .wrfull ( ),
+ .wrusedw ( wrusedw ) );
+
+ assign have_pkt_rdy = (rdusedw >= 12'd256);
+ assign have_space = (wrusedw < 12'd760);
+
+ // Rx side fifos
+ wire chan_rdreq;
+ wire [15:0] chan_fifodata;
+ wire [9:0] chan_usedw;
+ wire [NUM_CHAN:0] chan_empty;
+ wire [3:0] rd_select;
+ wire [NUM_CHAN:0] rx_full;
+
+ packet_builder #(NUM_CHAN) rx_pkt_builer (
+ .rxclk ( rxclk ),
+ .reset ( reset ),
+ .adctime ( adctime ),
+ .channels ( 4'd1 ),
+ .chan_rdreq ( chan_rdreq ),
+ .chan_fifodata ( chan_fifodata ),
+ .chan_empty ( chan_empty ),
+ .rd_select ( rd_select ),
+ .chan_usedw ( chan_usedw ),
+ .WR ( WR ),
+ .fifodata ( fifodata ),
+ .have_space ( have_space ) );
+
+ // Detect overrun
+ always @(posedge rxclk)
+ if(reset)
+ rx_overrun <= 1'b0;
+ else if(rx_full[0])
+ rx_overrun <= 1'b1;
+ else if(clear_status)
+ rx_overrun <= 1'b0;
+
+ reg [6:0] test;
+ always @(posedge rxclk)
+ if (reset)
+ test <= 0;
+ else
+ test <= test + 1;
+
+ // TODO write this genericly
+ wire [15:0]ch[NUM_CHAN:0];
+ assign ch[0] = ch_0;
+ assign ch[1] = rx_databus;//ch_1;
+
+ generate for (i = 0 ; i <= NUM_CHAN; i = i + 1)
+ begin : generate_channel_fifos
+ wire [15:0] dataout;
+ wire [9:0] usedw;
+ wire rdreq;
+
+ assign rdreq = (rd_select == i ? chan_rdreq : 1'd0);
+ assign chan_fifodata = (rd_select == i ? dataout : 16'bZ);
+ assign chan_usedw = (rd_select == i ? usedw : 10'bZ);
+ assign chan_empty[i] = (i == NUM_CHAN ? usedw < 10'd2 : usedw <
10'd126);
+
+ fifo_2k_1clk rx_chan_fifo (
+ .aclr ( reset ),
+ .clock ( rxclk ),
+ .data ( ch[i] ),
+ .rdreq ( rdreq ),
+ .wrreq ( ~rx_full[i] && ((rxstrobe && i < NUM_CHAN) ||
(i == NUM_CHAN && rx_WR)) ),
+ .empty ( ),
+ .full ( rx_full[i] ),
+ .q ( dataout ),
+ .usedw ( usedw ) );
+ end
+ endgenerate
+
+ assign debugbus = 0;
+endmodule
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-06-26 19:30:56 UTC (rev 5845)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-06-26 21:42:30 UTC (rev 5846)
@@ -2,7 +2,7 @@
( usbclk, bus_reset, reset, usbdata, WR, have_space,
tx_underrun, channels, tx_i_0, tx_q_0, tx_i_1, tx_q_1,
tx_i_2, tx_q_2, tx_i_3, tx_q_3, txclk, txstrobe,
- clear_status, tx_empty, debugbus
+ clear_status, tx_empty, debugbus, rx_databus, rx_WR
);
parameter NUM_CHAN = 2 ;
@@ -34,15 +34,24 @@
output wire [15:0] tx_q_2 ;
output wire [15:0] tx_i_3 ;
output wire [15:0] tx_q_3 ;
-
+ output wire [15:0] rx_databus ;
+ output wire rx_WR;
+
/* To generate channel readers */
genvar i ;
/* These will eventually be external register */
- reg [31:0] time_counter ;
+ reg [31:0] adc_time ;
wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
+ always @(posedge txclk)
+ if (reset)
+ adc_time <= 0;
+ else if (txstrobe)
+ adc_time <= adc_time + 1;
+
+
/* Connections between tx_usb_fifo_reader and
cnannel/command processing blocks */
wire [31:0] tx_data_bus ;
@@ -67,9 +76,8 @@
wire [15:0] tx_i [NUM_CHAN-1:0] ;
wire [15:0] tx_q [NUM_CHAN-1:0] ;
+ /* TODO: Figure out how to write this genericly */
assign have_space = chan_have_space[0] & chan_have_space[1];
-
- /* TODO: Figure out how to write this genericly */
assign tx_empty = chan_txempty[0] & chan_txempty[1] ;
assign tx_underrun = chan_underrun[0] | chan_underrun[1] ;
assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
@@ -131,7 +139,7 @@
( .reset (reset),
.tx_clock (txclk),
.tx_strobe (txstrobe),
- .adc_time (32'd0),
+ .adc_time (adc_time),
.samples_format (4'b0),
.tx_q (tx_q[i]),
.tx_i (tx_i[i]),
@@ -145,6 +153,35 @@
end
endgenerate
+
+
+ channel_ram tx_cmd_packet_fifo
+ ( .reset (reset),
+ .txclk (txclk),
+ .datain (tx_data_bus),
+ .WR (chan_WR[NUM_CHAN]),
+ .WR_done (chan_done[NUM_CHAN]),
+ .have_space (chan_have_space[NUM_CHAN]),
+ .dataout (chan_fifodata[NUM_CHAN]),
+ .packet_waiting (chan_pkt_waiting[NUM_CHAN]),
+ .RD (chan_rdreq[NUM_CHAN]),
+ .RD_done (chan_skip[NUM_CHAN])
+ );
+
+
+ cmd_reader tx_cmd_reader
+ ( .reset (reset),
+ .txclk (txclk),
+ .adc_time
(adc_time),
+ .skip
(chan_skip[NUM_CHAN]),
+ .rdreq
(chan_rdreq[NUM_CHAN]),
+ .fifodata
(chan_fifodata[NUM_CHAN]),
+ .pkt_waiting
(chan_pkt_waiting[NUM_CHAN]),
+ .rx_databus
(rx_databus),
+ .rx_WR (rx_WR)
+ );
+
+
endmodule // tx_buffer
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
2007-06-26 19:30:56 UTC (rev 5845)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
2007-06-26 21:42:30 UTC (rev 5846)
@@ -152,8 +152,10 @@
// Store channel and forware header
HEADER: begin
- channel <= (usbdata_final[`CHANNEL]) ;
- WR_channel[usbdata_final[`CHANNEL]] <= 1;
+ channel <= (usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN :
usbdata_final[`CHANNEL]) ;
+ WR_channel[(usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN :
usbdata_final[`CHANNEL])] <= 1;
+ //channel <= usbdata_final[`CHANNEL] ;
+ //WR_channel[usbdata_final[`CHANNEL]] <= 1;
ram_data <= usbdata_final;
read_length <= 10'd4 ;
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-06-26 19:30:56 UTC (rev 5845)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-06-26 21:42:30 UTC (rev 5846)
@@ -372,6 +372,7 @@
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition
-to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps"
+set_global_assignment -name VERILOG_FILE ../../inband_lib/cmd_reader.v
set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k_1clk.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/packet_builder.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/rx_buffer_inband.v
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-06-26 19:30:56 UTC (rev 5845)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-06-26 21:42:30 UTC (rev 5846)
@@ -19,7 +19,7 @@
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
-//`define TX_IN_BAND
+`define TX_IN_BAND
`define RX_IN_BAND
`include "config.vh"
@@ -116,6 +116,10 @@
reg [15:0] debug_counter;
reg [15:0] loopback_i_0,loopback_q_0;
+
+ //Connection RX inband <-> TX inband
+ wire rx_WR;
+ wire [15:0] rx_databus;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit Side
`ifdef TX_ON
@@ -136,7 +140,9 @@
.txclk(clk64),.txstrobe(strobe_interp),
.clear_status(clear_status),
.tx_empty(tx_empty),
- .debugbus(tx_debugbus) );
+ .debugbus(tx_debugbus),
+ .rx_WR(rx_WR),
+ .rx_databus(rx_databus) );
`else
tx_buffer tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
@@ -249,7 +255,9 @@
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
- .debugbus(rx_debugbus) );
+ .debugbus(rx_debugbus),
+ .rx_WR(rx_WR),
+ .rx_databus(rx_databus) );
`else
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/host/lib/inband/gen_test_packets.py
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/host/lib/inband/gen_test_packets.py
2007-06-26 19:30:56 UTC (rev 5845)
+++
gnuradio/branches/developers/thottelt/inband/usrp/host/lib/inband/gen_test_packets.py
2007-06-26 21:42:30 UTC (rev 5846)
@@ -70,7 +70,7 @@
lengths = gen_shuffled_lengths()
npkts = len(lengths) # number of packets we'll generator on
each stream
pkt_gen_0 = packet_sequence_generator(0, lengths)
- pkt_gen_1 = packet_sequence_generator(1, gen_shuffled_lengths())
+ pkt_gen_1 = packet_sequence_generator(0x1f, gen_shuffled_lengths())
pkt_gen = (pkt_gen_0, pkt_gen_1)
which_gen = (npkts * [0]) + (npkts * [1])
Modified:
gnuradio/branches/developers/thottelt/simulations/all_valid_packet_lengths_1_channel.dat
===================================================================
(Binary files differ)
Modified:
gnuradio/branches/developers/thottelt/simulations/all_valid_packet_lengths_2_channels.dat
===================================================================
(Binary files differ)
Modified: gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
2007-06-26 19:30:56 UTC (rev 5845)
+++ gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
2007-06-26 21:42:30 UTC (rev 5846)
@@ -24,7 +24,10 @@
wire [15:0]tx_i_3;
wire [15:0]tx_q_3;
wire ok;
+wire rx_WR;
+wire [15:0]rx_databus;
+
/* NOT USED YET */
reg clear_status;
reg channels;
@@ -50,7 +53,9 @@
.bus_reset(bus_reset),
.clear_status(1'b0),
.channels(4'b0),
- .debugbus()
+ .debugbus(),
+ .rx_WR(rx_WR),
+ .rx_databus(rx_databus)
);
strobe_gen strobe_gen_test(
@@ -72,8 +77,8 @@
);
initial begin
- //file = $fopen("all_valid_packet_lengths_2_channels.dat", "rb");
- file = $fopen("all_valid_packet_lengths_1_channel.dat", "rb");
+ file = $fopen("all_valid_packet_lengths_2_channels.dat", "rb");
+ //file = $fopen("all_valid_packet_lengths_1_channel.dat", "rb");
start = 0;
count = 0;
usbclock = 0;
Modified: gnuradio/branches/developers/thottelt/simulations/rx_fake_fx2.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/rx_fake_fx2.v
2007-06-26 19:30:56 UTC (rev 5845)
+++ gnuradio/branches/developers/thottelt/simulations/rx_fake_fx2.v
2007-06-26 21:42:30 UTC (rev 5846)
@@ -27,7 +27,7 @@
.RD(RD),
.have_pkt_rdy(have_pkt_rdy),
.rx_overrun(rx_overrun),
- .channels(channels),
+ .channels(4'd1),
.ch_0(ch_0),
.ch_1(ch_1),
.ch_2(),.ch_3(),.ch_4(),.ch_5(),.ch_6(),.ch_7(),
@@ -94,7 +94,7 @@
RCV: begin
count <= count + 1;
- if (usbdata != 16'hDEAD)
+ if (usbdata != 16'hDEAD && count < 256)
$display(usbdata);
if (count == 256)
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-26
19:30:56 UTC (rev 5845)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-26
21:42:30 UTC (rev 5846)
@@ -243,63 +243,65 @@
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
-Project_Files_Count = 28
-Project_File_0 = ./strobe_gen_test.v
-Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177269906 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_1 = ./usb_fifo_writer_test.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
14 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_2 = Z:/wc/inband/usrp/fpga/inband_lib/channel_ram.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575398 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_3 = Z:/wc/simulations/data_packet_fifo_test.v
-Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_4 = Z:/wc/simulations/fake_tx_chain.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_5 = Z:/wc/inband/usrp/fpga/megacells/fifo_2k.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
18 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_6 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_chain.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
20 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_7 = ./fake_fx2_test.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177428969 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_8 = ./fake_fx2.v
-Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575379 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
11 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_9 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
-Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575398 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_10 = Z:/wc/inband/usrp/fpga/inband_lib/packet_builder.v
-Project_File_P_10 = vlog_protect 0 cover_toggle 0 vhdl_novitalcheck 0
cover_exttoggle 0 file_type verilog group_id 0 vhdl_nodebug 0 vhdl_1164 1
cover_cond 0 vhdl_noload 0 vhdl_enable0In 0 vhdl_synth 0 vlog_1995compat 0
vlog_nodebug 0 vhdl_disableopt 0 last_compile 1182367979 folder {Top Level}
cover_branch 0 vlog_noload 0 vhdl_vital 0 vlog_enable0In 0 vhdl_warn1 1
vhdl_vopt 0 vlog_disableopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1
vhdl_0InOptions {} vhdl_warn3 1 vlog_optionfile Z:/wc/simulations/vlog.opt
vlog_vopt 0 vhdl_options {} vhdl_warn4 1 vlog_hazard 0 vlog_showsource 0 ood 0
vhdl_warn5 1 vlog_0InOptions {} compile_to work vlog_upper 0 vlog_options {}
compile_order 24 dont_compile 0 cover_nosub 0 cover_expr 0 vhdl_use93 2002
cover_stmt 0
-Project_File_11 = Z:/wc/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
-Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1182367408 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 23
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_12 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575461 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_13 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
-Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575398 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_14 = ./chan_fifo_readers_test.v
-Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575379 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 1
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_Files_Count = 29
+Project_File_0 = Z:/wc/inband/usrp/fpga/inband_lib/cmd_reader.v
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1182797882 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
28 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_1 = ./strobe_gen_test.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177269906 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_2 = ./usb_fifo_writer_test.v
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_3 = Z:/wc/inband/usrp/fpga/inband_lib/channel_ram.v
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575398 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
20 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_4 = Z:/wc/simulations/data_packet_fifo_test.v
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_5 = Z:/wc/simulations/fake_tx_chain.v
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
16 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_6 = Z:/wc/inband/usrp/fpga/megacells/fifo_2k.v
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_7 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_chain.v
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 19
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_8 = ./fake_fx2_test.v
+Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177428969 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
11 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_9 = Z:/wc/inband/usrp/fpga/megacells/fifo_4k.v
+Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 27
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_10 = ./fake_fx2.v
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1182889696 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
10 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_11 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575461 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_12 = Z:/wc/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1182889297 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
22 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_13 = Z:/wc/inband/usrp/fpga/inband_lib/packet_builder.v
+Project_File_P_13 = vlog_protect 0 cover_toggle 0 vhdl_novitalcheck 0
cover_exttoggle 0 file_type verilog group_id 0 vhdl_nodebug 0 vhdl_1164 1
cover_cond 0 vhdl_noload 0 vlog_1995compat 0 vlog_nodebug 0 vhdl_synth 0
vhdl_enable0In 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile
1182786842 vhdl_disableopt 0 vlog_enable0In 0 vhdl_vital 0 vlog_disableopt 0
vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0
vlog_vopt 0 vlog_optionfile Z:/wc/simulations/vlog.opt vhdl_warn3 1
vhdl_0InOptions {} vlog_showsource 0 vlog_hazard 0 vhdl_warn4 1 vhdl_options {}
vlog_0InOptions {} vhdl_warn5 1 ood 0 vlog_options {} vlog_upper 0 compile_to
work compile_order 23 cover_expr 0 cover_nosub 0 dont_compile 0 cover_stmt 0
vhdl_use93 2002
+Project_File_14 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
+Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1182889559 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_15 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
-Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181591850 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_16 = ../inband/usrp/fpga/megacells/fifo_1k.v
-Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1182351098 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_17 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v
-Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
19 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1182869402 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
12 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_16 = ./chan_fifo_readers_test.v
+Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575379 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_17 = ../inband/usrp/fpga/megacells/fifo_1k.v
+Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1182351098 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_18 = ./usb_packet_fifo_test.v
-Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177365360 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_19 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
-Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_20 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
-Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575398 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_21 = ./tx_buffer_test.v
-Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179008242 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_22 = Z:/wc/simulations/channel_ram_test.v
-Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_23 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
-Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177365360 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_19 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v
+Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_20 = ./tx_buffer_test.v
+Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179008242 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_21 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
+Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575398 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 7
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_22 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
+Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 5
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_23 = Z:/wc/simulations/rx_chains.v
+Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181852410 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
25 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_24 = Z:/wc/simulations/rx_fake_fx2.v
-Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1182363783 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 25
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_25 = Z:/wc/simulations/rx_chains.v
-Project_File_P_25 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181852410 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 26
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_26 = ./usb_fifo_reader_test.v
-Project_File_P_26 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178397904 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1182712519 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
24 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_25 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
+Project_File_P_25 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_26 = Z:/wc/simulations/channel_ram_test.v
+Project_File_P_26 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
21 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_27 = Z:/wc/inband/usrp/fpga/megacells/fifo_2k_1clk.v
-Project_File_P_27 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181850595 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
27 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_27 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181850595 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 26
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_28 = ./usb_fifo_reader_test.v
+Project_File_P_28 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178397904 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2
cover_expr 0 dont_compile 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
@@ -329,6 +331,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1} {Z:/wc/simulations/rx_fake_fx2.v 0 1}
{Z:/wc/inband/usrp/fpga/inband_lib/rx_buffer_inband.v 0 0}
+EditorState = {tabbed horizontal 1} {Z:/wc/simulations/fake_fx2.v 0 1}
Project_Major_Version = 6
Project_Minor_Version = 1
Modified: gnuradio/branches/developers/thottelt/simulations/work/_info
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/work/_info
2007-06-26 19:30:56 UTC (rev 5845)
+++ gnuradio/branches/developers/thottelt/simulations/work/_info
2007-06-26 21:42:30 UTC (rev 5846)
@@ -54,6 +54,58 @@
31
o-work work -O0
tGenerateLoopIterationMax 100000
+valt_inbuf
+Im8hdgKb4PTKK?SI:0F0ih2
+VG1eWzF9N`]U>W9m<kh2:=2
+dZ:\wc\simulations
+w1137746438
+FC:/altera/quartus51sp1/eda/sim_lib/altera_primitives.v
+L0 767
+VG1eWzF9N`]U>W9m<kh2:=2
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
+valt_iobuf
+ICAmljS9mIDJn8QDnDKGb]1
+V=cGzDfll2khX>@T[a986G1
+dZ:\wc\simulations
+w1137746438
+FC:/altera/quartus51sp1/eda/sim_lib/altera_primitives.v
+L0 805
+V=cGzDfll2khX>@T[a986G1
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
+valt_outbuf
+I56GM;address@hidden<S0
+VYPTQ6YP_3:aSUh05FFkKV3
+dZ:\wc\simulations
+w1137746438
+FC:/altera/quartus51sp1/eda/sim_lib/altera_primitives.v
+L0 778
+VYPTQ6YP_3:aSUh05FFkKV3
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
+valt_outbuf_tri
address@hidden<RjlL4nn3^DOf0
+Vje[oP?WiWf9n?ON1HKGZ;2
+dZ:\wc\simulations
+w1137746438
+FC:/altera/quartus51sp1/eda/sim_lib/altera_primitives.v
+L0 791
+Vje[oP?WiWf9n?ON1HKGZ;2
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
valtaccumulate
IT076a<TgU06<BG=6MXIjX1
V9Ul5<MUi1M<Q[bF:E9QnI3
@@ -394,6 +446,45 @@
31
o-work work -O0
tGenerateLoopIterationMax 100000
+vcarry
address@hidden
+VI2hZ[c0BXLj;RMfz_`dDM3
+dZ:\wc\simulations
+w1137746438
+FC:/altera/quartus51sp1/eda/sim_lib/altera_primitives.v
+L0 29
+VI2hZ[c0BXLj;RMfz_`dDM3
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
+vcarry_sum
+ILgGUA0k??kEHGzm7jXLR;1
address@hidden
+dZ:\wc\simulations
+w1137746438
+FC:/altera/quartus51sp1/eda/sim_lib/altera_primitives.v
+L0 45
address@hidden
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
+vcascade
+IOWOj3>=>29YhSW1z0MC7R2
+V;Vo8489M4<address@hidden
+dZ:\wc\simulations
+w1137746438
+FC:/altera/quartus51sp1/eda/sim_lib/altera_primitives.v
+L0 37
+V;Vo8489M4<address@hidden
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
vchan_fifo_reader
I8lC7lP92KA9UAz7X?[UMO2
VZ1@>;address@hidden
@@ -446,6 +537,410 @@
31
o-work work -O0
tGenerateLoopIterationMax 100000
+vclklock
+I6D^KGnRQ?j:A3dIYWbZVM3
address@hidden:2
+dZ:\wc\simulations
+w1137746438
+FC:/altera/quartus51sp1/eda/sim_lib/altera_primitives.v
+L0 378
address@hidden:2
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
+vcmd_reader
+IA7l8lQn_FE9e75lI6a44W3
address@hidden
+dZ:\wc\simulations
+w1182797882
+FZ:/wc/inband/usrp/fpga/inband_lib/cmd_reader.v
+L0 1
address@hidden
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
+vcyclone_and1
address@hidden<3
+VI5Qd:ff0KCB<CNFbW:zi61
+dZ:\wc\simulations
+w1137746522
+FC:/altera/quartus51sp1/eda/sim_lib/cyclone_atoms.v
+L0 273
+VI5Qd:ff0KCB<CNFbW:zi61
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
+vcyclone_and16
+ICC8M6biVD3FLP=9=jRNf02
+VRV7=616Y<mU=]CX637U3E0
+dZ:\wc\simulations
+w1137746522
+FC:/altera/quartus51sp1/eda/sim_lib/cyclone_atoms.v
+L0 286
+VRV7=616Y<mU=]CX637U3E0
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
+vcyclone_asmiblock
+IS_>5[FON;MmHnF;=?Mn793
+V]0LhOYf:Uj^<Wg;zZT_2c1
+dZ:\wc\simulations
+w1137746522
+FC:/altera/quartus51sp1/eda/sim_lib/cyclone_atoms.v
+L0 6755
+V]0LhOYf:Uj^<Wg;zZT_2c1
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
+vcyclone_asynch_io
+IW2nn3gBeFAMV67NZS5Jo[2
+V7=M]a5DDc8ZRkXGNN>cKJ2
+dZ:\wc\simulations
+w1137746522
+FC:/altera/quartus51sp1/eda/sim_lib/cyclone_atoms.v
+L0 6370
+V7=M]a5DDc8ZRkXGNN>cKJ2
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
+vcyclone_asynch_lcell
+ILoR[79`Da[^cOzZlB8TBM3
+VH`^jeC?eCb4^d<XPeXZ>>0
+dZ:\wc\simulations
+w1137746522
+FC:/altera/quartus51sp1/eda/sim_lib/cyclone_atoms.v
+L0 371
+VH`^jeC?eCb4^d<XPeXZ>>0
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
+vcyclone_b17mux21
+InB4G8?QL24dB]L`PV`L5d2
address@hidden
+dZ:\wc\simulations
+w1137746522
+FC:/altera/quartus51sp1/eda/sim_lib/cyclone_atoms.v
+L0 326
address@hidden
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
+vcyclone_b5mux21
+I5gX_l6;32lzRYERH2KYd_0
+VEI[?[>:FWj`S5UK<fC<1N3
+dZ:\wc\simulations
+w1137746522
+FC:/altera/quartus51sp1/eda/sim_lib/cyclone_atoms.v
+L0 347
+VEI[?[>:FWj`S5UK<fC<1N3
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
+vcyclone_bmux21
+IhH4WE1YfObfTeUJ1B?:XP2
address@hidden
+dZ:\wc\simulations
+w1137746522
+FC:/altera/quartus51sp1/eda/sim_lib/cyclone_atoms.v
+L0 315
address@hidden
+OV;L;6.1g;31
+r1
+31
+o-work work -O0
+tGenerateLoopIterationMax 100000
+vcyclone_crcblock
+IL<C2nF<G6`fCnEM<@[KlM3
+V?4>KJXz>S]DhHoPf83dmn1
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vdffp
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VNCKUEDQ^OBUgncngA<V;H2
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+Vm78k>c?EQ?URcg;address@hidden
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+r1
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+tGenerateLoopIterationMax 100000
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address@hidden
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vrx_buffer
IFWeJE95?VUV5jUYbfS;hJ1
VWl?3EIUZhCKiL8^PVXG<_2
@@ -1140,13 +1986,13 @@
o-work work -O0
tGenerateLoopIterationMax 100000
vrx_buffer_inband
-IUn3Rc[mogO^cAFhQH^T_H1
-V>address@hidden
address@hidden<<g0
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dZ:\wc\simulations
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FZ:/wc/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
L0 4
-V>address@hidden
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OV;L;6.1g;31
r1
31
@@ -1166,10 +2012,10 @@
o-work work -O0
tGenerateLoopIterationMax 100000
vrx_fake_fx2
-IngJk0L;L58jJ3>:address@hidden
address@hidden
V<Zz<:address@hidden:=9n>O:i3
dZ:\wc\simulations
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FZ:/wc/simulations/rx_fake_fx2.v
L0 1
V<Zz<:address@hidden:=9n>O:i3
@@ -1204,6 +2050,45 @@
31
o-work work -O0
tGenerateLoopIterationMax 100000
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vstratix_lvds_rx
IZ8X46RjcZT9hdYY_7Pz8]3
VfP2o;eO=6gjB:address@hidden<3
@@ -1334,6 +2219,46 @@
31
o-work work -O0
tGenerateLoopIterationMax 100000
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+L0 250
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address@hidden
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+L0 261
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+tGenerateLoopIterationMax 100000
+vTRI
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+V^6h=j:HebB6hGA5ka^Zcz2
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+L0 88
+V^6h=j:HebB6hGA5ka^Zcz2
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address@hidden@address@hidden
vtx_buffer
INMR7cLFjL_Q_6zHG9mZ`j0
V9;09Q[c9zC_7eOW:3L6I;3
@@ -1348,13 +2273,13 @@
o-work work -O0
tGenerateLoopIterationMax 100000
vtx_buffer_inband
-IDhmihSzW18GT0S7a>dzWW2
-VHg6Q3TO7C;[aX]AU=aUTV0
address@hidden;5jM0
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dZ:\wc\simulations
-w1181575398
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F../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
L0 1
-VHg6Q3TO7C;[aX]AU=aUTV0
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OV;L;6.1g;31
r1
31
@@ -1426,10 +2351,10 @@
o-work work -O0
tGenerateLoopIterationMax 100000
vusb_fifo_writer
-IjQGC]AgTnE7ccM6o[j8EV0
+IXK8aRE0cKFS3TiO=E^a9E1
VRaM8V7OA3zW<address@hidden
dZ:\wc\simulations
-w1181591850
+w1182869402
F../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
L0 2
VRaM8V7OA3zW<address@hidden
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