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[Commit-gnuradio] r5933 - in gnuradio/branches/developers/jcorgan/sar/gr
|
From: |
jcorgan |
|
Subject: |
[Commit-gnuradio] r5933 - in gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src: fpga/lib fpga/tb fpga/top python |
|
Date: |
Wed, 11 Jul 2007 13:02:38 -0600 (MDT) |
Author: jcorgan
Date: 2007-07-11 13:02:37 -0600 (Wed, 11 Jul 2007)
New Revision: 5933
Removed:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar_assignment_defaults.qdf
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar.v
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_control.v
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_tx.v
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/tb/sar_tb.sav
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/tb/sar_tb.v
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.qsf
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.rbf
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/sar.py
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/usrp_sar.py
Log:
Work in progress.
Modified: gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar.v
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar.v
2007-07-11 18:13:09 UTC (rev 5932)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar.v
2007-07-11 19:02:37 UTC (rev 5933)
@@ -49,7 +49,7 @@
wire tx_enable; // Transmitter enable
wire rx_enable; // Receiver enable
- wire [13:0] ampl;
+ wire [15:0] ampl;
wire [31:0] freq; // temporary
sar_control controller
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_control.v
===================================================================
---
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_control.v
2007-07-11 18:13:09 UTC (rev 5932)
+++
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_control.v
2007-07-11 19:02:37 UTC (rev 5933)
@@ -37,7 +37,7 @@
output tx_ena_o;
output rx_ena_o;
- output [13:0] ampl_o;
+ output [15:0] ampl_o;
output [31:0] freq_o;
// Internal configuration
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_tx.v
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_tx.v
2007-07-11 18:13:09 UTC (rev 5932)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_tx.v
2007-07-11 19:02:37 UTC (rev 5933)
@@ -27,7 +27,7 @@
input strobe_i;
// Configuration
- input [13:0] ampl_i;
+ input [15:0] ampl_i;
input [31:0] freq_i;
// Output
@@ -37,10 +37,10 @@
wire [15:0] cordic_i, cordic_q;
cordic_nco
nco(.clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(strobe_i),
- .ampl_i({ampl_i,2'b00}),.freq_i(freq_i),.phs_i(0),
+ .ampl_i(ampl_i),.freq_i(freq_i),.phs_i(0),
.data_i_o(cordic_i),.data_q_o(cordic_q));
- assign tx_i_o = cordic_i[15:2];
- assign tx_q_o = cordic_q[15:2];
+ assign tx_i_o = cordic_i[13:0];
+ assign tx_q_o = cordic_q[13:0];
endmodule // sar_tx
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/tb/sar_tb.sav
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/tb/sar_tb.sav
2007-07-11 18:13:09 UTC (rev 5932)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/tb/sar_tb.sav
2007-07-11 19:02:37 UTC (rev 5933)
@@ -1,4 +1,4 @@
-*-20.535921 4787000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 -1 -1 -1
+*-20.535921 1109000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 -1 -1 -1
@28
sar_tb.clk
sar_tb.ena
@@ -10,7 +10,8 @@
-
@24
sar_tb.uut.freq[31:0]
-sar_tb.uut.controller.ampl_o[13:0]
address@hidden
+sar_tb.uut.controller.ampl_o[15:0]
@200
-
@28
@@ -20,5 +21,3 @@
sar_tb.uut.tx_dac_q_o[13:0]
@200
-
address@hidden
-sar_tb.uut.transmitter.nco.phase[31:0]
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/tb/sar_tb.v
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/tb/sar_tb.v
2007-07-11 18:13:09 UTC (rev 5932)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/tb/sar_tb.v
2007-07-11 19:02:37 UTC (rev 5933)
@@ -164,7 +164,7 @@
task test_tx;
begin
#20 set_reset(1);
- #20 set_amplitude(14'h2000);
+ #20 set_amplitude(16'd9946);
#20 set_frequency(32'h08000000);
#20 enable_tx(1);
#20 enable_rx(0);
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.qsf
===================================================================
---
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.qsf
2007-07-11 18:13:09 UTC (rev 5932)
+++
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.qsf
2007-07-11 19:02:37 UTC (rev 5933)
@@ -1,15 +1,15 @@
-# Copyright (C) 1991-2005 Altera Corporation
+# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
@@ -23,11 +23,35 @@
# and any changes you make may be lost or overwritten.
+
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13,
2003"
set_global_assignment -name LAST_QUARTUS_VERSION 7.0
+set_global_assignment -name VERILOG_FILE usrp_sar.v
+set_global_assignment -name VERILOG_FILE dacpll.v
+set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v
+set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
+set_global_assignment -name VERILOG_FILE ../lib/sar_control.v
+set_global_assignment -name VERILOG_FILE ../lib/sar_rx.v
+set_global_assignment -name VERILOG_FILE ../lib/sar_tx.v
+set_global_assignment -name VERILOG_FILE ../lib/sar.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/adc_interface.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/atr_delay.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/bidir_reg.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/clk_divider.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/cordic_stage.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/gen_sync.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/io_pins.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/master_control.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_buffer.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/serial_io.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/setting_reg.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/strobe_gen.v
# Pin & Location Assignments
# ==========================
@@ -206,9 +230,10 @@
set_location_assignment PIN_194 -to io_tx_a[15]
set_location_assignment PIN_1 -to MYSTERY_SIGNAL
-# Timing Assignments
-# ==================
+# Classic Timing Assignments
+# ==========================
set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS
OFF
+set_global_assignment -name MAX_SCC_SIZE 50
# Analysis & Synthesis Assignments
# ================================
@@ -220,10 +245,10 @@
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name TOP_LEVEL_ENTITY usrp_sar
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name USER_LIBRARIES
"h:\\gnuradio\\trunk\\usrp\\fpga\\megacells"
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
+set_global_assignment -name TOP_LEVEL_ENTITY usrp_sar
# Fitter Assignments
# ==================
@@ -235,7 +260,7 @@
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_global_assignment -name INC_PLC_MODE OFF
set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
@@ -243,10 +268,6 @@
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-# Timing Analysis Assignments
-# ===========================
-set_global_assignment -name MAX_SCC_SIZE 50
-
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
@@ -265,7 +286,7 @@
# Simulator Assignments
# =====================
set_global_assignment -name START_TIME "0 ns"
-set_global_assignment -name GLITCH_INTERVAL "1 ns"
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
# Design Assistant Assignments
# ============================
@@ -309,6 +330,8 @@
set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
set_global_assignment -name HCPY_CAT OFF
set_global_assignment -name HCPY_VREF_PINS OFF
+set_global_assignment -name ENABLE_DA_RULE "C101, C102, C103, C104, C105,
C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105,
A106, A107, A108, A109, A110, S101, S102, D101, D102, D103, H102"
+set_global_assignment -name DISABLE_DA_RULE H101
# SignalTap II Assignments
# ========================
@@ -320,35 +343,35 @@
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
+# start CLOCK(SCLK)
# -----------------
-# start CLOCK(SCLK)
- # Timing Assignments
- # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
-set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
+ # Classic Timing Assignments
+ # ==========================
+ set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
+ set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
# end CLOCK(SCLK)
# ---------------
+# start CLOCK(master_clk)
# -----------------------
-# start CLOCK(master_clk)
- # Timing Assignments
- # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
-set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
+ # Classic Timing Assignments
+ # ==========================
+ set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
+ set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id
master_clk
# end CLOCK(master_clk)
# ---------------------
+# start CLOCK(usbclk)
# -------------------
-# start CLOCK(usbclk)
- # Timing Assignments
- # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
-set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
+ # Classic Timing Assignments
+ # ==========================
+ set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
+ set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
# end CLOCK(usbclk)
# -----------------
@@ -356,39 +379,22 @@
# ----------------------
# start ENTITY(usrp_sar)
- # Timing Assignments
- # ==================
-set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
-set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
-set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
+ # Classic Timing Assignments
+ # ==========================
+ set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
+ set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
+ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
-# end ENTITY(usrp_sar)
-# --------------------
+ # start DESIGN_PARTITION(Top)
+ # ---------------------------
-set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition
-to | -section_id Top
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+ # Incremental Compilation Assignments
+ # ===================================
+ set_instance_assignment -name PARTITION_HIERARCHY
no_file_for_top_partition -to | -section_id Top
+ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE
-section_id Top
-set_global_assignment -name VERILOG_FILE usrp_sar.v
-set_global_assignment -name VERILOG_FILE dacpll.v
-set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v
-set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
-set_global_assignment -name VERILOG_FILE ../lib/sar_control.v
-set_global_assignment -name VERILOG_FILE ../lib/sar_rx.v
-set_global_assignment -name VERILOG_FILE ../lib/sar_tx.v
-set_global_assignment -name VERILOG_FILE ../lib/sar.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/adc_interface.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/atr_delay.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/bidir_reg.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/clk_divider.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/cordic_stage.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/gen_sync.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/io_pins.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/master_control.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_buffer.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/setting_reg.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/strobe_gen.v
-set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE usrp_sar.srf
\ No newline at end of file
+ # end DESIGN_PARTITION(Top)
+ # -------------------------
+
+# end ENTITY(usrp_sar)
+# --------------------
\ No newline at end of file
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.rbf
===================================================================
(Binary files differ)
Deleted:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar_assignment_defaults.qdf
Modified: gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/sar.py
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/sar.py
2007-07-11 18:13:09 UTC (rev 5932)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/sar.py
2007-07-11 19:02:37 UTC (rev 5933)
@@ -41,7 +41,7 @@
#FR_SAR_TSW = usrp.FR_USER_2 # 16-bit transmitter switch time in
clocks
#FR_SAR_TLOOK = usrp.FR_USER_3 # 16-bit receiver look time in clocks
#FR_SAR_TIDLE = usrp.FR_USER_4 # 32-bit inter-pulse idle time
-FR_SAR_AMPL = usrp.FR_USER_5 # 14-bit pulse amplitude (2s complement)
+FR_SAR_AMPL = usrp.FR_USER_5 # 16-bit pulse amplitude (2s complement) into
CORDIC
#FR_SAR_FSTART = usrp.FR_USER_6 # 32-bit FTW for chirp start frequency
#FR_SAR_FINCR = usrp.FR_USER_7 # 32-bit FTW increment per transmit clock
@@ -87,7 +87,7 @@
self._u._write_fpga_reg(FR_SAR_FREQ1N, self._ftw)
def set_amplitude(self, ampl):
- self._amplitude = ampl
+ self._amplitude = int(ampl*9946/100.0) # CORDIC gain correction
if self._debug:
print "Writing amplitude register with:", hex(self._amplitude)
self._u._write_fpga_reg(FR_SAR_AMPL, self._amplitude)
@@ -95,7 +95,9 @@
def start(self):
self._u.start()
-
+ def stop(self):
+ self._u.stop()
+
#-----------------------------------------------------------------------
# Receiver object. Uses usrp_source_c to receive echo records.
# NOT IMPLEMENTED YET
@@ -179,7 +181,7 @@
self._transmitting = False
self._trans = sar_tx(verbose=self._verbose, debug=self._debug)
self.set_reset(True)
-
+
def set_amplitude(self, ampl):
self._trans.set_amplitude(ampl)
@@ -241,13 +243,16 @@
self._write_mode()
def start(self):
- self.enable_tx(True)
+ self._trans.start()
+ self.enable_tx(True)
self.set_reset(False)
-
+
def stop(self):
- if self._transmitting:
- self.enable_tx(False)
- self.set_reset(True)
+ self.set_reset(True)
+ self.enable_tx(False)
+ self._trans.stop()
+ #if self._transmitting:
+ # self.enable_tx(False)
def __del__(self):
self.stop()
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/usrp_sar.py
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/usrp_sar.py
2007-07-11 18:13:09 UTC (rev 5932)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/usrp_sar.py
2007-07-11 19:02:37 UTC (rev 5933)
@@ -34,10 +34,10 @@
parser.add_option("-f", "--frequency", type="eng_float", default=0.0,
help="set transmitter center frequency to FREQ in Hz,
default is %default", metavar="FREQ")
# Temporary for debugging transmitter frequency response
- parser.add_option("-w", "--waveform-frequency", type="eng_float",
default=0.0,
+ parser.add_option("-w", "--waveform-frequency", type="eng_float",
default=1e3,
help="set waveform offset frequency to FREQ in Hz,
default is %default", metavar="FREQ")
- parser.add_option("-a", "--amplitude", type="int", default=4096,
- help="set waveform amplitude, default is %default,")
+ parser.add_option("-a", "--amplitude", type="eng_float", default=100,
+ help="set waveform amplitude in % full scale, default is
%default,")
parser.add_option("-v", "--verbose", action="store_true", default=False,
help="enable verbose output, default is disabled")
parser.add_option("-D", "--debug", action="store_true", default=False,
@@ -91,6 +91,7 @@
"""
raw_input("Press enter to stop transmitting.")
-
+ s.stop()
+
if __name__ == "__main__":
main()
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- [Commit-gnuradio] r5933 - in gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src: fpga/lib fpga/tb fpga/top python,
jcorgan <=