[Commit-gnuradio] r5937 - in gnuradio/branches/developers/matt/u2f/top: . u2_fpga

[matt]

Author: matt
Date: 2007-07-11 14:13:58 -0600 (Wed, 11 Jul 2007)
New Revision: 5937

Modified:
   gnuradio/branches/developers/matt/u2f/top/
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj
Log:
progress



Property changes on: gnuradio/branches/developers/matt/u2f/top
___________________________________________________________________
Name: svn:ignore
   + *.sav


Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
===================================================================
(Binary files differ)

Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj   
2007-07-11 20:13:29 UTC (rev 5936)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj   
2007-07-11 20:13:58 UTC (rev 5937)
@@ -16,11 +16,14 @@
 verilog work "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_core.v"
 verilog work "../../control_lib/strobe_gen.v"
+verilog work "../../control_lib/ss_rcvr.v"
 verilog work "../../control_lib/shortfifo.v"
 verilog work "../../control_lib/setting_reg.v"
+verilog work "../../control_lib/ram_2port.v"
+verilog work "../../control_lib/mux8.v"
+verilog work "../../control_lib/mux4.v"
 verilog work "../../control_lib/fifo_int.v"
 verilog work "../../control_lib/decoder_3_8.v"
-verilog work "../../control_lib/buffer_2k.v"
 verilog work "../../control_lib/CRC16_D16.v"
 verilog work "../../sdr_lib/dsp_core_tx.v"
 verilog work "../../sdr_lib/dsp_core_rx.v"
@@ -28,7 +31,6 @@
 verilog work "../../opencores/simple_gpio/rtl/simple_gpio.v"
 verilog work "../../opencores/i2c/rtl/verilog/i2c_master_top.v"
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v"
-verilog work "../../control_lib/wb_output_pins32.v"
 verilog work "../../control_lib/wb_1master.v"
 verilog work "../../control_lib/system_control.v"
 verilog work "../../control_lib/settings_bus.v"