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[Commit-gnuradio] r5946 - in gnuradio/branches/developers/jcorgan/radar:
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From: |
jcorgan |
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Subject: |
[Commit-gnuradio] r5946 - in gnuradio/branches/developers/jcorgan/radar: config gr-radar-mono/src/fpga/lib gr-radar-mono/src/fpga/tb gr-radar-mono/src/fpga/top |
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Date: |
Thu, 12 Jul 2007 09:28:11 -0600 (MDT) |
Author: jcorgan
Date: 2007-07-12 09:28:08 -0600 (Thu, 12 Jul 2007)
New Revision: 5946
Modified:
gnuradio/branches/developers/jcorgan/radar/config/Makefile.am
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/cordic_nco.v
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar.v
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_control.v
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb/
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb/radar_tb.sav
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb/radar_tb.v
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
Log:
Work in progress. New Quartus 7.1SP1. Generate tx_strobe from within radar
controller. Misc. cleanups.
Modified: gnuradio/branches/developers/jcorgan/radar/config/Makefile.am
===================================================================
--- gnuradio/branches/developers/jcorgan/radar/config/Makefile.am
2007-07-12 00:58:04 UTC (rev 5945)
+++ gnuradio/branches/developers/jcorgan/radar/config/Makefile.am
2007-07-12 15:28:08 UTC (rev 5946)
@@ -46,7 +46,6 @@
grc_gr_radar_mono.m4 \
grc_gr_radio_astronomy.m4 \
grc_gr_rdf.m4 \
- grc_gr_radar_mono.m4 \
grc_gr_sounder.m4 \
grc_gr_trellis.m4 \
grc_gr_usrp.m4 \
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/cordic_nco.v
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/cordic_nco.v
2007-07-12 00:58:04 UTC (rev 5945)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/cordic_nco.v
2007-07-12 15:28:08 UTC (rev 5946)
@@ -47,7 +47,7 @@
assign ampl = ena_i ? ampl_i : 16'b0;
cordic tx_cordic
- (.clock(clk_i),.reset(rst_in),.enable(strobe_i),
+ (.clock(clk_i),.reset(rst_i),.enable(strobe_i),
.xi(ampl),.yi(16'b0),.zi(phase[31:16]),
.xo(data_i_o),.yo(data_q_o),.zo());
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar.v
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar.v
2007-07-12 00:58:04 UTC (rev 5945)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar.v
2007-07-12 15:28:08 UTC (rev 5946)
@@ -22,7 +22,7 @@
`include "../lib/radar_config.vh"
module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
- tx_strobe_i,tx_dac_i_o,tx_dac_q_o,
+ tx_strobe_o,tx_dac_i_o,tx_dac_q_o,
rx_strobe_i,rx_adc_i_i,rx_adc_q_i,
rx_strobe_o,rx_ech_i_o,rx_ech_q_o);
@@ -33,7 +33,7 @@
input s_strobe_i; // Configuration bus write
// Transmit subsystem
- input tx_strobe_i; // Generate an transmitter output sample
+ output tx_strobe_o; // Generate an transmitter output sample
output [13:0] tx_dac_i_o; // I channel transmitter output to DAC
output [13:0] tx_dac_q_o; // Q channel transmitter output to DAC
@@ -51,17 +51,16 @@
wire [15:0] ampl;
wire [31:0] freq; // temporary
-
+
radar_control controller
- (.clk_i(clk_i),.rst_i(1'b0),.ena_i(1'b1),
- .s_strobe_i(s_strobe_i),.saddr_i(saddr_i),.sdata_i(sdata_i),
+
(.clk_i(clk_i),.s_strobe_i(s_strobe_i),.saddr_i(saddr_i),.sdata_i(sdata_i),
.reset_o(reset),.tx_ena_o(tx_enable),.rx_ena_o(rx_enable),
- .ampl_o(ampl),.freq_o(freq));
+ .ampl_o(ampl),.freq_o(freq),.tx_strobe_o(tx_strobe_o));
radar_tx transmitter
( .clk_i(clk_i),.rst_i(reset),.ena_i(tx_enable),
.ampl_i(ampl),.freq_i(freq),
- .strobe_i(tx_strobe_i),.tx_i_o(tx_dac_i_o),.tx_q_o(tx_dac_q_o) );
+ .strobe_i(tx_strobe_o),.tx_i_o(tx_dac_i_o),.tx_q_o(tx_dac_q_o) );
radar_rx receiver
( .clk_i(clk_i),.rst_i(reset),.ena_i(rx_enable),
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_control.v
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_control.v
2007-07-12 00:58:04 UTC (rev 5945)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_control.v
2007-07-12 15:28:08 UTC (rev 5946)
@@ -21,13 +21,12 @@
`include "../lib/radar_config.vh"
-module radar_control(clk_i,rst_i,ena_i,saddr_i,sdata_i,s_strobe_i,
- reset_o,tx_ena_o,rx_ena_o,ampl_o,freq_o);
+module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
+ reset_o,tx_ena_o,rx_ena_o,ampl_o,freq_o,
+ tx_strobe_o);
// System interface
input clk_i; // Master clock @ 64 MHz
- input rst_i; // Master reset
- input ena_i; // Module level enable
input [6:0] saddr_i; // Configuration bus address
input [31:0] sdata_i; // Configuration bus data
input s_strobe_i; // Configuration bus write
@@ -40,20 +39,36 @@
output [15:0] ampl_o;
output [31:0] freq_o;
+ // Control signal outputs
+ output tx_strobe_o;
+
// Internal configuration
wire lp_ena;
wire dr_ena;
wire md_ena;
wire [1:0] chirps;
+ // Master control state machine
+ reg [31:0] phase;
+
// Configuration from host
- setting_reg #(`FR_RADAR_MODE)
sr_mode(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
-
.out({chirps,md_ena,dr_ena,lp_ena,rx_ena_o,tx_ena_o,reset_o}));
+ setting_reg #(`FR_RADAR_MODE)
sr_mode(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
+
.out({chirps,md_ena,dr_ena,lp_ena,rx_ena_o,tx_ena_o,reset_o}));
- setting_reg #(`FR_RADAR_AMPL)
sr_ampl(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
- .out(ampl_o));
+ setting_reg #(`FR_RADAR_AMPL)
sr_ampl(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
+ .out(ampl_o));
- setting_reg #(`FR_RADAR_FREQ1N)
sr_freq(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
- .out(freq_o));
+ setting_reg #(`FR_RADAR_FREQ1N)
sr_freq(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
+ .out(freq_o));
+
+ // Master time base
+ always @(posedge clk_i)
+ if (reset_o)
+ phase <= 32'b0;
+ else
+ phase <= phase + 32'b1;
+ // 32 MHz
+ assign tx_strobe_o = phase[0];
+
endmodule // radar_control
Property changes on:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb
___________________________________________________________________
Name: svn:ignore
- Makefile
Makefile.in
sar_tb
out
*.out*
*.vcd
+ Makefile
Makefile.in
radar_tb
out
*.out*
*.vcd
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb/radar_tb.sav
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb/radar_tb.sav
2007-07-12 00:58:04 UTC (rev 5945)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb/radar_tb.sav
2007-07-12 15:28:08 UTC (rev 5946)
@@ -1,4 +1,4 @@
-*-20.535921 1109000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 -1 -1 -1
+*-20.514782 1460000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 -1 -1 -1
@28
radar_tb.clk
radar_tb.ena
@@ -10,7 +10,7 @@
-
@24
radar_tb.uut.freq[31:0]
address@hidden
address@hidden
radar_tb.uut.controller.ampl_o[15:0]
@200
-
@@ -21,3 +21,5 @@
radar_tb.uut.tx_dac_q_o[13:0]
@200
-
address@hidden
+radar_tb.uut.controller.phase[31:0]
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb/radar_tb.v
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb/radar_tb.v
2007-07-12 00:58:04 UTC (rev 5945)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb/radar_tb.v
2007-07-12 15:28:08 UTC (rev 5946)
@@ -36,7 +36,7 @@
reg s_strobe;
// DAC bus
- reg tx_strobe;
+ wire tx_strobe;
wire [13:0] tx_dac_i;
wire [13:0] tx_dac_q;
@@ -55,14 +55,10 @@
radar uut
(.clk_i(clk),.saddr_i(saddr),.sdata_i(sdata),.s_strobe_i(s_strobe),
- .tx_strobe_i(tx_strobe),.tx_dac_i_o(tx_dac_i),.tx_dac_q_o(tx_dac_q),
+ .tx_strobe_o(tx_strobe),.tx_dac_i_o(tx_dac_i),.tx_dac_q_o(tx_dac_q),
.rx_strobe_i(rx_strobe),.rx_adc_i_i(rx_adc_i),.rx_adc_q_i(rx_adc_q),
.rx_strobe_o(fifo_strobe),.rx_ech_i_o(fifo_i),.rx_ech_q_o(fifo_q));
- // Drive tx_strobe @ half clock rate
- always @(posedge clk)
- tx_strobe <= ~tx_strobe;
-
// Start up initialization
initial
begin
@@ -72,7 +68,6 @@
saddr = 0;
sdata = 0;
s_strobe = 0;
- tx_strobe = 0;
rx_strobe = 1;
rx_adc_i = 0;
rx_adc_q = 0;
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
2007-07-12 00:58:04 UTC (rev 5945)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
2007-07-12 15:28:08 UTC (rev 5946)
@@ -28,7 +28,7 @@
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13,
2003"
-set_global_assignment -name LAST_QUARTUS_VERSION 7.0
+set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1"
set_global_assignment -name VERILOG_FILE usrp_radar_mono.v
set_global_assignment -name VERILOG_FILE dacpll.v
set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v
@@ -397,4 +397,5 @@
# -------------------------
# end ENTITY(usrp_radar_mono)
-# --------------------
\ No newline at end of file
+# --------------------
+set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE usrp_radar_mono.srf
\ No newline at end of file
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf
===================================================================
(Binary files differ)
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
2007-07-12 00:58:04 UTC (rev 5945)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
2007-07-12 15:28:08 UTC (rev 5946)
@@ -0,0 +1,130 @@
+{ "Warning" "WSGN_SEARCH_FILE"
"../../../../../trunk/usrp/fpga/megacells/bustri.v 1 1 " "Warning: Using design
file ../../../../../trunk/usrp/fpga/megacells/bustri.v, which is not specified
as a design file for the current project, but contains definitions for 1 design
units and 1 entities in project" { } { } 0 0 "Using design file %1!s!, which
is not specified as a design file for the current project, but contains
definitions for %2!d! design units and %3!d! entities in project" 1 0 "" 0}
+{ "Warning" "WSGN_SEARCH_FILE"
"../../../../../trunk/usrp/fpga/megacells/fifo_4k.v 10 10 " "Warning: Using
design file ../../../../../trunk/usrp/fpga/megacells/fifo_4k.v, which is not
specified as a design file for the current project, but contains definitions
for 10 design units and 10 entities in project" { } { } 0 0 "Using design
file %1!s!, which is not specified as a design file for the current project,
but contains definitions for %2!d! design units and %3!d! entities in project"
1 0 "" 0}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "write_done
serial_io.v(48) " "Warning (10036): Verilog HDL or VHDL warning at
serial_io.v(48): object \"write_done\" assigned a value but never read" { } {
{ "../../../../usrp/fpga/sdr_lib/serial_io.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/serial_io.v" 48 0 0 } } } 0 10036
"Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but
never read" 1 0 "" 0}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(58)
" "Warning (10230): Verilog HDL assignment warning at atr_delay.v(58):
truncated value with size 32 to match size of target (12)" { } { {
"../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 58 0 0 } } } 0 10230
"Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to
match size of target (%2!d!)" 1 0 "" 0}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(71)
" "Warning (10230): Verilog HDL assignment warning at atr_delay.v(71):
truncated value with size 32 to match size of target (12)" { } { {
"../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 71 0 0 } } } 0 10230
"Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to
match size of target (%2!d!)" 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rx_delay 12 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_rx_delay\" is
connected to a signal of width 12. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rx_delay" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 138 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_tx_delay 12 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_tx_delay\" is
connected to a signal of width 12. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_tx_delay" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 137 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_3 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_3\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_3" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 134 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_3 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_3\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_3" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 133 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_3 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_3\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_3" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 132 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_2 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_2\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_2" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 130 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_2 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_2\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_2" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 129 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_2 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_2\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_2" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 128 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_1 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_1\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_1" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 126 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_1 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_1\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_1" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 125 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_1 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_1\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_1" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 124 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_0 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_0\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_0" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 122 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_0 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_0\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_0" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 121 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_0 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_0\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_0" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 120 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_3 7 8 "
"Warning: Port \"ratio\" on the entity instantiation of \"clk_div_3\" is
connected to a signal of width 7. The formal width of the signal in the module
is 8. Extra bits will be driven by GND." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_3" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 98 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be driven by GND." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_2 7 8 "
"Warning: Port \"ratio\" on the entity instantiation of \"clk_div_2\" is
connected to a signal of width 7. The formal width of the signal in the module
is 8. Extra bits will be driven by GND." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_2" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 97 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be driven by GND." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_1 7 8 "
"Warning: Port \"ratio\" on the entity instantiation of \"clk_div_1\" is
connected to a signal of width 7. The formal width of the signal in the module
is 8. Extra bits will be driven by GND." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_1" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 96 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be driven by GND." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_0 7 8 "
"Warning: Port \"ratio\" on the entity instantiation of \"clk_div_0\" is
connected to a signal of width 7. The formal width of the signal in the module
is 8. Extra bits will be driven by GND." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_0" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 95 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be driven by GND." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_debugen 4 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_debugen\" is connected to a
signal of width 4. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_debugen" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 93 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxbref 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_rxbref\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_rxbref" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 91 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_txbref 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_txbref\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_txbref" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 90 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxaref 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_rxaref\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_rxaref" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 89 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_txaref 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_txaref\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_txaref" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 88 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_decim 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_decim\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_decim" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 51 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_interp 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_interp\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_interp" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 50 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mstr_ctrl 8 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_mstr_ctrl\" is
connected to a signal of width 8. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_mstr_ctrl" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 42 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "rate rx_strobe_gen 32
8 " "Warning: Port \"rate\" on the entity instantiation of \"rx_strobe_gen\" is
connected to a signal of width 32. The formal width of the signal in the module
is 8. Extra bits will be ignored." { } { { "../lib/radar_rx.v"
"rx_strobe_gen" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_rx.v" 62 0 0 } } } 0 0
"Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage11 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage11\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage11" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 100 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage10 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage10\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage10" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 99 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage9 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage9\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage9" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 98 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage8 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage8\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage8" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 97 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage7 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage7\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage7" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 96 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage6 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage6\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage6" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 95 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage5 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage5\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage5" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 94 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage4 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage4\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage4" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 93 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage3 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage3\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage3" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 92 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage2 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage2\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage2" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 91 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage1 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage1\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage1" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 90 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage0 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage0\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage0" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 89 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a
signal of width 16. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_ampl" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 59 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mode 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_mode\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_mode" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 56 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Warning: The following nets
are missing source, defaulting to GND" { } { } 0 0 "The following nets are
missing source, defaulting to GND" 1 0 "" 0}
+{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Warning: The following nets
are missing source, defaulting to GND" { { "Warning"
"WSGN_TRI_BUS_MISSING_SOURCE_SUB"
"radar:radar_mono\|radar_control:controller\|rst_i " "Warning: Net
\"radar:radar_mono\|radar_control:controller\|rst_i\"" { } { {
"../lib/radar_control.v" "rst_i" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 55 -1 0 } } } 0
0 "Net \"%1!s!\"" 1 0 "" 0} } { } 0 0 "The following nets are missing source,
defaulting to GND" 0 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxformat 11 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_rxformat\" is
connected to a signal of width 11. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/rx_buffer.v" "sr_rxformat" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/rx_buffer.v" 66 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxmux 20 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_rxmux\" is connected to a
signal of width 20. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/adc_interface.v" "sr_rxmux" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/adc_interface.v" 54 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_dco_en 4 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_dco_en\" is connected to a
signal of width 4. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/adc_interface.v" "sr_dco_en" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/adc_interface.v" 32 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[3\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[3\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[4\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[4\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[5\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[5\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[6\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[6\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[7\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[7\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[8\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[8\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[9\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[9\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[10\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[10\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[11\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[11\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[12\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[12\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[13\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[13\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[14\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[14\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[15\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[15\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[16\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[16\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[17\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[17\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"master_control:master_control\|atr_delay:atr_delay\|state.0001 data_in GND "
"Warning: Reduced register
\"master_control:master_control\|atr_delay:atr_delay\|state.0001\" with stuck
data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 31 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "MYSTERY_SIGNAL GND " "Warning: Pin
\"MYSTERY_SIGNAL\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 24 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "FX2_3 GND " "Warning: Pin \"FX2_3\"
stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 33 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[0\] GND " "Warning: Pin
\"tx_b\[0\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[1\] GND " "Warning: Pin
\"tx_b\[1\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[2\] GND " "Warning: Pin
\"tx_b\[2\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[3\] GND " "Warning: Pin
\"tx_b\[3\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[4\] GND " "Warning: Pin
\"tx_b\[4\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[5\] GND " "Warning: Pin
\"tx_b\[5\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[6\] GND " "Warning: Pin
\"tx_b\[6\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[7\] GND " "Warning: Pin
\"tx_b\[7\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[8\] GND " "Warning: Pin
\"tx_b\[8\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[9\] GND " "Warning: Pin
\"tx_b\[9\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[10\] GND " "Warning: Pin
\"tx_b\[10\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[11\] GND " "Warning: Pin
\"tx_b\[11\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[12\] GND " "Warning: Pin
\"tx_b\[12\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[13\] GND " "Warning: Pin
\"tx_b\[13\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "TXSYNC_B GND " "Warning: Pin
\"TXSYNC_B\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 44 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "usbrdy\[0\] GND " "Warning: Pin
\"usbrdy\[0\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 49 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[0\] " "Warning: No output dependent
on input pin \"rx_b_a\[0\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[1\] " "Warning: No output dependent
on input pin \"rx_b_a\[1\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[2\] " "Warning: No output dependent
on input pin \"rx_b_a\[2\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[3\] " "Warning: No output dependent
on input pin \"rx_b_a\[3\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[4\] " "Warning: No output dependent
on input pin \"rx_b_a\[4\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[5\] " "Warning: No output dependent
on input pin \"rx_b_a\[5\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[6\] " "Warning: No output dependent
on input pin \"rx_b_a\[6\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[7\] " "Warning: No output dependent
on input pin \"rx_b_a\[7\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[8\] " "Warning: No output dependent
on input pin \"rx_b_a\[8\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[9\] " "Warning: No output dependent
on input pin \"rx_b_a\[9\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[10\] " "Warning: No output dependent
on input pin \"rx_b_a\[10\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[11\] " "Warning: No output dependent
on input pin \"rx_b_a\[11\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[0\] " "Warning: No output dependent
on input pin \"rx_b_b\[0\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[1\] " "Warning: No output dependent
on input pin \"rx_b_b\[1\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[2\] " "Warning: No output dependent
on input pin \"rx_b_b\[2\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[3\] " "Warning: No output dependent
on input pin \"rx_b_b\[3\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[4\] " "Warning: No output dependent
on input pin \"rx_b_b\[4\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[5\] " "Warning: No output dependent
on input pin \"rx_b_b\[5\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[6\] " "Warning: No output dependent
on input pin \"rx_b_b\[6\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[7\] " "Warning: No output dependent
on input pin \"rx_b_b\[7\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[8\] " "Warning: No output dependent
on input pin \"rx_b_b\[8\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[9\] " "Warning: No output dependent
on input pin \"rx_b_b\[9\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[10\] " "Warning: No output dependent
on input pin \"rx_b_b\[10\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[11\] " "Warning: No output dependent
on input pin \"rx_b_b\[11\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "MYSTERY_SIGNAL GND " "Info:
Pin MYSTERY_SIGNAL has GND driving its datain port" { } { {
"usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 24 -1 0 } } {
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "MYSTERY_SIGNAL" }
} } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MYSTERY_SIGNAL
} "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" ""
{ Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
MYSTERY_SIGNAL } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain
port" 1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC
driving datain port -- changes to this connectivity may change fitting results"
0 0 "" 0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FX2_3 GND " "Info: Pin FX2_3
has GND driving its datain port" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 33 -1 0 } } {
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FX2_3" } } } } {
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FX2_3 }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
FX2_3 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1
0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[0\] GND " "Info: Pin
tx_b\[0\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[0\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[0] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[1\] GND " "Info: Pin
tx_b\[1\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[1\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[1] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[2\] GND " "Info: Pin
tx_b\[2\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[2\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[2] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[3\] GND " "Info: Pin
tx_b\[3\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[3\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[3] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[4\] GND " "Info: Pin
tx_b\[4\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[4\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[4] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[5\] GND " "Info: Pin
tx_b\[5\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[5\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[5] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[6\] GND " "Info: Pin
tx_b\[6\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[6\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[6] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[7\] GND " "Info: Pin
tx_b\[7\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[7\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[7] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[8\] GND " "Info: Pin
tx_b\[8\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[8\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[8] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[9\] GND " "Info: Pin
tx_b\[9\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[9\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[9] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[10\] GND " "Info: Pin
tx_b\[10\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[10\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[10] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[11\] GND " "Info: Pin
tx_b\[11\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[11\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[11] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[12\] GND " "Info: Pin
tx_b\[12\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[12\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[12] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[13\] GND " "Info: Pin
tx_b\[13\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[13\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[13] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TXSYNC_B GND " "Info: Pin
TXSYNC_B has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 44 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TXSYNC_B" } } } }
{ "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { TXSYNC_B }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
TXSYNC_B } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "usbrdy\[0\] GND " "Info: Pin
usbrdy\[0\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 49 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "usbrdy\[0\]" } }
} } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { usbrdy[0] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
usbrdy[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain
port" 1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC
driving datain port -- changes to this connectivity may change fitting results"
0 0 "" 0}
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
2007-07-12 00:58:04 UTC (rev 5945)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
2007-07-12 15:28:08 UTC (rev 5946)
@@ -142,7 +142,7 @@
// Top level application
radar radar_mono (
.clk_i(clk64),.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
- .tx_strobe_i(tx_sample_strobe),.tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q),
+ .tx_strobe_o(tx_sample_strobe),.tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q),
.rx_strobe_i(rx_sample_strobe),.rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q),
.rx_strobe_o(rx_strobe),.rx_ech_i_o(rx_buf_i),.rx_ech_q_o(rx_buf_q)
);
@@ -172,7 +172,7 @@
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(),.decim_rate(),
- .tx_sample_strobe(tx_sample_strobe),.strobe_interp(),
+ .tx_sample_strobe(),.strobe_interp(), // tx_sample_strobe now generated
by radar transmitter module
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(),
.tx_empty(tx_empty),
.debug_0(),.debug_1(),
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- [Commit-gnuradio] r5946 - in gnuradio/branches/developers/jcorgan/radar: config gr-radar-mono/src/fpga/lib gr-radar-mono/src/fpga/tb gr-radar-mono/src/fpga/top,
jcorgan <=