[Commit-gnuradio] r5997 - gnuradio/branches/developers/matt/u2f/top/u2_basic

[matt]

Author: matt
Date: 2007-07-17 11:44:14 -0600 (Tue, 17 Jul 2007)
New Revision: 5997

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Log:
hookups for buffer status readback and interrupts


Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-07-17 17:42:53 UTC (rev 5996)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-07-17 17:44:14 UTC (rev 5997)
@@ -124,7 +124,9 @@
    wire        ram_loader_rst, wb_rst, dsp_rst;
 
    wire [31:0]         ser_debug;
-   
+
+   wire [31:0]         status, status_b0, status_b1, status_b2, status_b3, 
status_b4, status_b5, status_b6, status_b7;
+ 
    // 
///////////////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Single Master INTERCON
    parameter   dw = 32;  // Data bus width
@@ -216,7 +218,6 @@
           .sys_int_i(proc_int),.sys_exc_i(bus_error) );
 
    assign       bus_error = m0_err | m0_rty;
-   assign       proc_int = 1'b0;
    
    // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
    // I-port connects directly to processor and ram loader
@@ -254,6 +255,11 @@
    
       .stream_clk(dsp_clk), .stream_rst(dsp_rst),
       .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .status(status),.sys_int_o(proc_int),
+
+      .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
+      .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7),
+      
       // Write Interfaces
       .wr0_dat_i(wr0_dat), .wr0_write_i(wr0_write), .wr0_done_i(wr0_done),
       .wr0_error_i(wr0_error), .wr0_ready_o(wr0_ready), .wr0_full_o(wr0_full),
@@ -290,7 +296,7 @@
      i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
          .wb_adr_i(s3_adr),.wb_dat_i(s3_dat_o),.wb_dat_o(s3_dat_i),
          .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
-         .wb_ack_o(s3_ack),.wb_inta_o(st_int),
+         .wb_ack_o(s3_ack),.wb_inta_o(s3_int),
          
.scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
          
.sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
    
@@ -324,8 +330,22 @@
    assign       s4_err = 1'b0;
    assign       s4_rty = 1'b0;
 
-   // Unused slave, #5
-   assign       s5_ack = s5_stb;
+   // Buffer Pool Control #5
+   
+   wb_readback_mux buff_pool_status
+     (.wb_clk_i(wb_clk),
+      .wb_rst_i(wb_rst),
+      .wb_stb_i(s5_stb),
+      .wb_adr_i(s5_adr),
+      .wb_dat_o(s5_dat_i),
+      .wb_ack_o(s5_ack),
+      
+      
.word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
+      
.word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
+      .word08(status),.word09(),.word10(),.word11(),
+      .word12(),.word13(),.word14(),.word15()
+      );
+
    assign       s5_err = 1'b0;
    assign       s5_rty = 1'b0;
 
@@ -353,13 +373,13 @@
    
    setting_reg #(.my_addr(0)) sr_clk 
(.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
                                      
.in(set_data),.out(clock_outs),.changed());
-   setting_reg #(.my_addr(1)) sr_ser 
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+/*   setting_reg #(.my_addr(1)) sr_ser 
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
                                      
.in(set_data),.out(serdes_outs),.changed());
    setting_reg #(.my_addr(2)) sr_adc 
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
                                      .in(set_data),.out(adc_outs),.changed());
    setting_reg #(.my_addr(3)) sr_led 
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
                                      .in(set_data),.out(misc_outs),.changed());
-
+*/
    // /////////////////////////////////////////////////////////////////////////
    // DSP
    reg [13:0]   adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
@@ -433,9 +453,3 @@
    assign      debug_clk[1] = dsp_clk; 
    
 endmodule // u2_basic
-
-// Local Variables:
-// verilog-library-directories:("." "subdir" "subdir2")
-// 
verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v")
-// verilog-library-extensions:(".v" ".h")
-// End: