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[Commit-gnuradio] r6172 - in gnuradio/branches/developers/matt/u2f/eth:


From: matt
Subject: [Commit-gnuradio] r6172 - in gnuradio/branches/developers/matt/u2f/eth: . bench/verilog rtl/verilog rtl/verilog/RMON rtl/verilog/TECH/xilinx
Date: Thu, 23 Aug 2007 16:46:35 -0600 (MDT)

Author: matt
Date: 2007-08-23 16:46:35 -0600 (Thu, 23 Aug 2007)
New Revision: 6172

Added:
   gnuradio/branches/developers/matt/u2f/eth/bench/verilog/100m.scr
   gnuradio/branches/developers/matt/u2f/eth/bench/verilog/error.scr
   gnuradio/branches/developers/matt/u2f/eth/bench/verilog/files.lst
   gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/RMON/RMON_ctrl.v
Removed:
   gnuradio/branches/developers/matt/u2f/eth/MAC_top.v
   gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/RMON/RMON_CTRL.v
Modified:
   gnuradio/branches/developers/matt/u2f/eth/bench/verilog/jumbos.scr
   gnuradio/branches/developers/matt/u2f/eth/bench/verilog/misc.scr
   gnuradio/branches/developers/matt/u2f/eth/bench/verilog/pause.scr
   gnuradio/branches/developers/matt/u2f/eth/bench/verilog/tb_top.v
   gnuradio/branches/developers/matt/u2f/eth/bench/verilog/test.scr
   gnuradio/branches/developers/matt/u2f/eth/mac_txfifo_int.v
   gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/Phy_int.v
   gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/RMON.v
   gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/Reg_int.v
   
gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/TECH/xilinx/RAMB16_S36_S36.v
Log:
from claus


Deleted: gnuradio/branches/developers/matt/u2f/eth/MAC_top.v

Added: gnuradio/branches/developers/matt/u2f/eth/bench/verilog/100m.scr
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/bench/verilog/100m.scr            
                (rev 0)
+++ gnuradio/branches/developers/matt/u2f/eth/bench/verilog/100m.scr    
2007-08-23 22:46:35 UTC (rev 6172)
@@ -0,0 +1,38 @@
+// This tests just runs a few packets at 10/100 Mbps and 1 Gbps instead of 
only the usual 1 Gbps
+
+// Read from register 24 to confirm that Rx CRC check is enabled
+03 00 18 00 01 ff ff
+
+// Set speed to 1000 Mbps for a starter
+01 00 22 00 04
+
+// Setup Tx and Rx MAC addresses and type field to "IP"
+// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
+10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
+
+// Transmit a 1000-byte frame 1 time - and expect it to be received again!
+20 03 E8 00 01
+
+// Wait (indefinitely) for missing Rx packets
+22 00 00 
+
+// Set speed to 100 Mbps - this is 10x slower!
+01 00 22 00 02
+
+// Transmit a 1000-byte frame 1 time - and expect it to be received again!
+20 03 E8 00 01
+
+// Wait (indefinitely) for missing Rx packets
+22 00 00 
+
+// Set speed to 10 Mbps - this is yet another 10x slower!
+01 00 22 00 01
+
+// Transmit a 1000-byte frame 1 time - and expect it to be received again!
+20 03 E8 00 01
+
+// Wait (indefinitely) for missing Rx packets
+22 00 00 
+
+// Halt
+FF

Added: gnuradio/branches/developers/matt/u2f/eth/bench/verilog/error.scr
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/bench/verilog/error.scr           
                (rev 0)
+++ gnuradio/branches/developers/matt/u2f/eth/bench/verilog/error.scr   
2007-08-23 22:46:35 UTC (rev 6172)
@@ -0,0 +1,76 @@
+// This tests sends 5 packets, injecting a bit error in two of them
+// to verify the Rx CRC check works. The corresponding RMON statistics
+// counter is finally checked to verify that the error was registered
+
+// Read from register 24 to confirm that Rx CRC check is enabled
+03 00 18 00 01 ff ff
+
+// Set speed to 1000 Mbps
+01 00 22 00 04
+
+// Setup Tx and Rx MAC addresses and type field to "IP"
+// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
+10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
+
+// Transmit a 200-byte frame 1 time - and expect it to be received again!
+20 00 C8 00 01
+
+// Wait (indefinitely) for missing Rx packets
+22 00 00 
+
+// Transmit a 200-byte frame 1 time - but don't expect it to be received again!
+21 00 C8 00 01
+
+// Inject a single bit error in the packet!!!
+23
+
+// Wait (indefinitely) for missing Rx packets
+22 00 00 
+
+// Transmit a 200-byte frame 1 time - and expect it to be received again!
+20 00 C8 00 01
+
+// Wait (indefinitely) for missing Rx packets
+22 00 00 
+
+// Transmit a 200-byte frame 1 time - but don't expect it to be received again!
+21 00 C8 00 01
+
+// Inject a single bit error in the packet!!!
+23
+
+// Wait (indefinitely) for missing Rx packets
+22 00 00 
+
+// Transmit a 200-byte frame 1 time - and expect it to be received again!
+20 00 C8 00 01
+
+// Wait (indefinitely) for missing Rx packets
+22 00 00 
+
+// Set CPU_rd_addr to address RxCRCErrCounter
+01 00 1C 00 05
+
+// Assert CPU_rd_apply
+01 00 1D 00 01
+
+// Kill a little time while waiting for CPU_rd_grant to assert...
+02 00 1E
+02 00 1E
+02 00 1E
+02 00 1E
+
+// Confirm that CPU_rd_grant is asserted
+03 00 1E 00 01 ff ff
+
+// Read & check low part of RxCRCErrCounter (0x0002)
+03 00 1F 00 02 ff ff
+
+// Read & check high part of RxCRCErrCounter (0x0000)
+03 00 20 00 00 ff ff
+
+// Negate CPU_rd_apply
+01 00 1D 00 00
+
+// Halt
+FF

Added: gnuradio/branches/developers/matt/u2f/eth/bench/verilog/files.lst
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/bench/verilog/files.lst           
                (rev 0)
+++ gnuradio/branches/developers/matt/u2f/eth/bench/verilog/files.lst   
2007-08-23 22:46:35 UTC (rev 6172)
@@ -0,0 +1,42 @@
+../../rtl/verilog/MAC_rx/Broadcast_filter.v
+../../rtl/verilog/MAC_rx/CRC_chk.v
+../../rtl/verilog/MAC_rx/MAC_rx_add_chk.v
+../../rtl/verilog/MAC_rx/MAC_rx_ctrl.v
+../../rtl/verilog/MAC_rx/MAC_rx_FF.v
+
+../../rtl/verilog/MAC_tx/CRC_gen.v
+../../rtl/verilog/MAC_tx/flow_ctrl.v
+../../rtl/verilog/MAC_tx/MAC_tx_addr_add.v
+../../rtl/verilog/MAC_tx/MAC_tx_ctrl.v
+../../rtl/verilog/MAC_tx/MAC_tx_FF.v
+../../rtl/verilog/MAC_tx/Ramdon_gen.v
+
+../../rtl/verilog/miim/eth_clockgen.v
+../../rtl/verilog/miim/eth_outputcontrol.v
+../../rtl/verilog/miim/eth_shiftreg.v
+
+../../rtl/verilog/RMON/RMON_addr_gen.v
+../../rtl/verilog/RMON/RMON_ctrl.v
+../../rtl/verilog/RMON/RMON_dpram.v
+
+../../rtl/verilog/TECH/duram.v
+../../rtl/verilog/TECH/eth_clk_div2.v
+../../rtl/verilog/TECH/eth_clk_switch.v
+
+../../rtl/verilog/TECH/xilinx/BUFGMUX.v
+../../rtl/verilog/TECH/xilinx/RAMB16_S36_S36.v
+
+../../rtl/verilog/Clk_ctrl.v
+../../rtl/verilog/eth_miim.v
+../../rtl/verilog/MAC_rx.v
+../../rtl/verilog/MAC_top.v
+../../rtl/verilog/MAC_tx.v
+../../rtl/verilog/Phy_int.v
+../../rtl/verilog/Reg_int.v
+../../rtl/verilog/RMON.v
+
+../../bench/verilog/Phy_sim.v
+../../bench/verilog/User_int_sim.v
+../../bench/verilog/host_sim.v
+../../bench/verilog/xlnx_glbl.v
+../../bench/verilog/tb_top.v

Modified: gnuradio/branches/developers/matt/u2f/eth/bench/verilog/jumbos.scr
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/bench/verilog/jumbos.scr  
2007-08-23 18:53:51 UTC (rev 6171)
+++ gnuradio/branches/developers/matt/u2f/eth/bench/verilog/jumbos.scr  
2007-08-23 22:46:35 UTC (rev 6172)
@@ -1,8 +1,8 @@
 // This test performs transmission & reception of several Jumbo-frames of 
~2Kbytes each
 // At the same time it demonstrates the wire-speed capabilities of the core
 
-// Read from register 0 and expect 9 - just a test...
-03 00 00 00 09 ff ff
+// Read from register 24 to confirm that Rx CRC check is enabled
+03 00 18 00 01 ff ff
 
 // Set speed to 1000 Mbps
 01 00 22 00 04

Modified: gnuradio/branches/developers/matt/u2f/eth/bench/verilog/misc.scr
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/bench/verilog/misc.scr    
2007-08-23 18:53:51 UTC (rev 6171)
+++ gnuradio/branches/developers/matt/u2f/eth/bench/verilog/misc.scr    
2007-08-23 22:46:35 UTC (rev 6172)
@@ -1,24 +1,92 @@
-// This tests just runs trough a couple of different packet lengths
-// - it also uses the MAC address filter
+// Read from register 24 to confirm that Rx CRC check is enabled
+03 00 18 00 01 ff ff
 
-// Read from register 0 and expect 9 - just a test...
-03 00 00 00 09 ff ff
-
 // Set speed to 1000 Mbps
 01 00 22 00 04
 
+// Write MAC address 12 35 56 78 9A BC to Rx Address buffer
+01 00 10 00 00
+01 00 0f 00 12
+01 00 11 00 01
+01 00 11 00 00
+01 00 10 00 01
+01 00 0f 00 34
+01 00 11 00 01
+01 00 11 00 00
+01 00 10 00 02
+01 00 0f 00 56
+01 00 11 00 01
+01 00 11 00 00
+01 00 10 00 03
+01 00 0f 00 78
+01 00 11 00 01
+01 00 11 00 00
+01 00 10 00 04
+01 00 0f 00 9A
+01 00 11 00 01
+01 00 11 00 00
+01 00 10 00 05
+01 00 0f 00 BC
+01 00 11 00 01
+01 00 11 00 00
+
+// Write 1 to register 14, MAC_rx_add_chk_e
+// This turns on the Rx Destination MAC address filter
+01 00 0e 00 01
+
 // Setup Tx and Rx MAC addresses and type field to "IP"
 // Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
+// (i.e. Destination MAC address is 123456789ABC matching the above)
 10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
 
-// Transmit a 200-byte frame 1 time - and expect it to be received again!
-20 01 00 00 01
-
+// Transmit a 60-byte frame 1 time - and expect it to be received again!
+20 00 3C 00 01
+// Transmit a 61-byte frame 1 time - and expect it to be received again!
+20 00 3D 00 01
+// Transmit a 62-byte frame 1 time - and expect it to be received again!
+20 00 3E 00 01
+// Transmit a 63-byte frame 1 time - and expect it to be received again!
+20 00 3F 00 01
 // Transmit a 64-byte frame 1 time - and expect it to be received again!
-20 00 3C 00 01
+20 00 40 00 01
 
+// Transmit a 500-byte frame 1 time - and expect it to be received again!
+20 01 4C 00 01
+
+// Transmit a 1500-byte frame 1 time - and expect it to be received again!
+20 05 DC 00 01
+
+// Transmit a 1514-byte frame 1 time - and expect it to be received again!
+20 05 EA 00 01
+
+// Transmit a 60-byte frame 3 times - and expect them to be received again!
+20 00 3C 00 03
+// Transmit a 61-byte frame 3 times - and expect them to be received again!
+20 00 3D 00 03
+// Transmit a 62-byte frame 3 times - and expect them to be received again!
+20 00 3E 00 03
+// Transmit a 63-byte frame 3 times - and expect them to be received again!
+20 00 3F 00 03
+// Transmit a 64-byte frame 3 times - and expect them to be received again!
+20 00 40 00 03
+
+// Transmit a 1510-byte frame 1 time - and expect it to be received again!
+20 05 E6 00 01
+
 // Wait (indefinitely) for missing Rx packets
 22 00 00 
 
-// Halt
-FF
+// Change Tx MAC to something different - we won't receive frames with this ID
+10 00 00 00 06 11 22 33 44 55 66
+
+// Transmit a 60 byte frame 3 times - but don't expect them to be received!
+21 00 3C 00 03
+
+//// Change Tx MAC back to 12 34 56 78 9A BC
+10 00 00 00 06 12 34 56 78 9A BC
+
+// Transmit a 60 byte frame 3 times - and expect them to be received again!
+20 00 3C 00 03
+
+// Wait (indefinitely) for missing Rx packets
+22 00 00 

Modified: gnuradio/branches/developers/matt/u2f/eth/bench/verilog/pause.scr
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/bench/verilog/pause.scr   
2007-08-23 18:53:51 UTC (rev 6171)
+++ gnuradio/branches/developers/matt/u2f/eth/bench/verilog/pause.scr   
2007-08-23 22:46:35 UTC (rev 6172)
@@ -1,8 +1,8 @@
 // This test demonstrates the ability to transmit a PAUSE frame, and the 
effect of
 // a PAUSE frame on the receiver
 
-// Read from register 0 and expect 9 - just a test...
-03 00 00 00 09 ff ff
+// Read from register 24 to confirm that Rx CRC check is enabled
+03 00 18 00 01 ff ff
 
 // Set speed to 1000 Mbps
 01 00 22 00 04
@@ -12,7 +12,7 @@
 10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
 
 // Set PAUSE quanta to 256 - corresponding to a pause of 256x512 = 128Kb = 16KB
-01 00 03 00 10
+01 00 03 01 00
 
 // Enable the transmitter to send a PAUSE frame
 01 00 02 00 01
@@ -20,22 +20,23 @@
 // Enable the transmitter to react to received PAUSE frames
 01 00 0b 00 01
 
-// Transmit a 512-byte frame 3 times - and expect them to be received again!
-20 02 00 00 03
-// - now do it a second time...
-// Transmit a 512-byte frame 3 times - and expect them to be received again!
-//20 02 00 00 03
+// Expect to receive a PAUSE frame with quanta 256
+24 01 00
 
+// Transmit a 512-byte frame 1 time - and expect it to be received again!
+20 02 00 00 01
+
 // Request the transmission of a PAUSE frame - it will loopback to ourselves 
and delay
-// further transmission for a period of 16 KB!
+// further transmission for a period of 16 KB, causing a significant (visible) 
delay
+// between first and second 512-byte frame!
 01 00 0c 00 01
 
-// - now this third time, we will experience a delay
-// Transmit a 512-byte frame 3 times - and expect them to be received again!
-20 02 00 00 03
-// - and a final 4th time
-// Transmit a 512-byte frame 3 times - and expect them to be received again!
-//20 02 00 00 03
+// - now this second time, we will experience a delay
+// Transmit a 512-byte frame 1 time - and expect it to be received again!
+20 02 00 00 01
+// - and a final 3rd time
+// Transmit a 512-byte frame 1 time - and expect it to be received again!
+20 02 00 00 01
 
 // Wait (indefinitely) for missing Rx packets
 22 00 00 

Modified: gnuradio/branches/developers/matt/u2f/eth/bench/verilog/tb_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/bench/verilog/tb_top.v    
2007-08-23 18:53:51 UTC (rev 6171)
+++ gnuradio/branches/developers/matt/u2f/eth/bench/verilog/tb_top.v    
2007-08-23 22:46:35 UTC (rev 6172)
@@ -97,8 +97,8 @@
   reg         Tx_mac_wr = 0;
   reg  [31:0] Tx_mac_data = 32'bx;
   reg  [1:0]  Tx_mac_BE = 2'bx;
-  reg         Tx_mac_sop = 0;
-  reg         Tx_mac_eop = 0;
+  reg         Tx_mac_sop = 1'bx;
+  reg         Tx_mac_eop = 1'bx;
 
   // PHY interface (GMII/MII)
   wire        Gtx_clk;
@@ -178,13 +178,18 @@
     .Mdc        ( Mdc  )
   );
 
+  reg        InjectError;
+  reg        InjectErrorDone;
+  reg [7:0]  TxError;
+  wire [7:0] TxdModified;
+
   Phy_sim U_Phy_sim(
     .Gtx_clk( Gtx_clk ),
     .Rx_clk ( Rx_clk  ),
     .Tx_clk ( Tx_clk  ),
     .Tx_er  ( Tx_er   ),
     .Tx_en  ( Tx_en   ),
-    .Txd    ( Txd     ),
+    .Txd    ( TxdModified ),
     .Rx_er  ( Rx_er   ),
     .Rx_dv  ( Rx_dv   ),
     .Rxd    ( Rxd     ),
@@ -194,6 +199,41 @@
     .Done   ( Done    )
   );
 
+  integer TxTrackPreAmble;
+
+  always @( posedge Reset or posedge Tx_clk )
+    if ( Reset )
+      TxTrackPreAmble <= 0;
+    else
+      if ( ~Tx_en )
+        TxTrackPreAmble <= 0;
+      else
+        TxTrackPreAmble <= TxTrackPreAmble + 1;
+
+  // Asserted after the Destination MAC address in the packet
+  wire TxInPayload = Tx_en & (TxTrackPreAmble > (7+6));
+  assign TxdModified = Txd ^ ( TxError & {8{TxInPayload}} );
+
+  always @( posedge Reset or posedge Tx_clk )
+    if ( Reset )
+      begin
+        InjectError <= 0;
+        InjectErrorDone <= 0;
+        TxError <= 8'b0;
+      end
+    else
+      if ( InjectError )
+        begin
+          InjectError <= 0;
+          TxError <= 8'h01;
+          InjectErrorDone <= TxInPayload;
+        end
+      else if ( TxInPayload || InjectErrorDone )
+        begin
+          TxError <= 8'h00;
+          InjectErrorDone <= 0;
+        end
+
   //-------------------------------------------------------------------------
   // Host access routines (register read & write)
   //-------------------------------------------------------------------------
@@ -333,6 +373,9 @@
   `define TXDATALEN 8000
   reg [7:0] TxData[0:`TXDATALEN-1];
 
+  // By default change payload after Ethernet Header
+  reg [15:0] TxHeaderLength = 14;
+
   real    TxStartTime;
   integer TxPacketCount = 0;
   integer TxByteCount;
@@ -343,6 +386,7 @@
 
     reg [15:0] Counter;
     integer    TxIndex;
+    integer    i;
 
     begin
       @( posedge Clk_user ); #1;
@@ -369,7 +413,12 @@
           Tx_mac_data[23:16] = TxData[ TxIndex+1 ];
           Tx_mac_data[15:8]  = TxData[ TxIndex+2 ];
           Tx_mac_data[ 7:0]  = TxData[ TxIndex+3 ];
-          TxIndex = TxIndex+4;
+          for ( i=0; i<4; i=i+1 )
+            begin
+              if ( TxIndex >= TxHeaderLength )
+                TxData[ TxIndex ] = TxData[ TxIndex ] + 1;
+              TxIndex = TxIndex+1;
+            end
 
           if ( Counter<=4 )
             begin
@@ -380,6 +429,11 @@
                 Tx_mac_BE = Counter;
               Tx_mac_eop = 1;
             end
+          else
+            begin
+              Tx_mac_BE = 2'b00;
+              Tx_mac_eop = 0;
+            end
 
           if ( Wr2FIFO )
             begin
@@ -399,7 +453,8 @@
           Tx_mac_sop = 0;
         end
 
-      Tx_mac_eop = 0;
+      Tx_mac_sop = 1'bx;
+      Tx_mac_eop = 1'bx;
       Tx_mac_wr = 0;
       Tx_mac_data = 32'bx;
       Tx_mac_BE   = 2'bx;
@@ -408,10 +463,12 @@
 
   //-------------------------------------------------------------------------
 
+  reg Negate_Rx_mac_rd;
+
   always @( posedge Clk_user or posedge Reset )
     if ( Reset )
       Rx_mac_rd <= 0;
-    else if ( Rx_mac_ra )
+    else if ( Rx_mac_ra & ~Negate_Rx_mac_rd )
       Rx_mac_rd <= 1;
     else
       Rx_mac_rd <= 0;
@@ -428,69 +485,77 @@
       begin
         InPacket = 0;
         RxPacketCount = 0;
+        Negate_Rx_mac_rd <= 0;
       end
     else
-      if ( Rx_mac_pa )
-        begin : RxWord
-          reg [35:0] RxData;
-          reg [35:0] Expected;
-          reg [35:0] Mask;
+      begin
+        Negate_Rx_mac_rd <= 0;
 
-          RxData = { Rx_mac_sop, Rx_mac_eop, Rx_mac_BE, Rx_mac_data };
-          casez ( Rx_mac_BE )
-            2'b01:   Mask = 36'hfff000000;
-            2'b10:   Mask = 36'hfffff0000;
-            2'b11:   Mask = 36'hfffffff00;
-            default: Mask = 36'hfffffffff;
-          endcase
+        if ( Rx_mac_pa )
+          begin : RxWord
+            reg [35:0] RxData;
+            reg [35:0] Expected;
+            reg [35:0] Mask;
 
-          // Retrieve expected packet data
-          FIFO_Rd( Expected );
+            RxData = { Rx_mac_sop, Rx_mac_eop, Rx_mac_BE, Rx_mac_data };
+            casez ( Rx_mac_BE )
+              2'b01:   Mask = 36'hfff000000;
+              2'b10:   Mask = 36'hfffff0000;
+              2'b11:   Mask = 36'hfffffff00;
+              default: Mask = 36'hfffffffff;
+            endcase
 
-          if ( (RxData & Mask) != (Expected & Mask) )
-            begin
-              $display( "ERROR: Receiving unexpected packet data: Got 0x%0x, 
expected 0x%0x (Mask=0x%0x)",
-                        RxData, Expected, Mask );
-              Error = 1;
-            end
+            // Retrieve expected packet data
+            FIFO_Rd( Expected );
 
-          if ( InPacket )
-            begin
-              if ( Rx_mac_eop )
-                begin
-                  if ( Rx_mac_BE==2'b00 )
-                    RxPacketLength = RxPacketLength + 4;
-                  else
-                    RxPacketLength = RxPacketLength + Rx_mac_BE;
-                  $display( "Rx packet #%0d of length %0d ends",
-                            RxPacketCount,
-                            RxPacketLength );
-                  RxPacketCount = RxPacketCount + 1;
-                  RxByteCount = RxByteCount + RxPacketLength;
-                  InPacket = 0;
-                end
-              else
-                RxPacketLength = RxPacketLength + 4;
-            end
-          else
-            begin
-              if ( Rx_mac_sop )
-                begin
-                  RxPacketLength = 4;
-                  $display( "Rx packet #%0d begins: 0x%08x", RxPacketCount, 
Rx_mac_data );
-                  InPacket = 1;
-                  if ( RxStartTime == 0 )
-                    RxStartTime = $realtime;
-                end
-              else
-                begin
-                  $display( "ERROR: Unexpectedly reading from Rx FIFO while 
not receiving a packet!" );
-                  Error = 1;
-                end
-            end
+            //$display( "DEBUG: RxData=0x%0x, Expected=0x%0x", RxData, 
Expected );
 
-        end
+            if ( (RxData & Mask) !== (Expected & Mask) )
+              begin
+                $display( "ERROR: Receiving unexpected packet data: Got 0x%0x, 
expected 0x%0x (Mask=0x%0x)",
+                          RxData, Expected, Mask );
+                Error = 1;
+              end
 
+            if ( InPacket )
+              begin
+                if ( Rx_mac_eop )
+                  begin
+                    // Ensure Rx_mac_rd is negated for one clock
+                    Negate_Rx_mac_rd <= 1;
+                    if ( Rx_mac_BE==2'b00 )
+                      RxPacketLength = RxPacketLength + 4;
+                    else
+                      RxPacketLength = RxPacketLength + Rx_mac_BE;
+                    $display( "Rx packet #%0d of length %0d ends",
+                              RxPacketCount,
+                              RxPacketLength );
+                    RxPacketCount = RxPacketCount + 1;
+                    RxByteCount = RxByteCount + RxPacketLength;
+                    InPacket = 0;
+                  end
+                else
+                  RxPacketLength = RxPacketLength + 4;
+              end
+            else
+              begin
+                if ( Rx_mac_sop )
+                  begin
+                    RxPacketLength = 4;
+                    $display( "Rx packet #%0d begins: 0x%08x", RxPacketCount, 
Rx_mac_data );
+                    InPacket = 1;
+                    if ( RxStartTime == 0 )
+                      RxStartTime = $realtime;
+                  end
+                else
+                  begin
+                    $display( "ERROR: Unexpectedly reading from Rx FIFO while 
not receiving a packet!" );
+                    Error = 1;
+                  end
+              end
+          end
+      end
+
   //-------------------------------------------------------------------------
   // Script handling
   //-------------------------------------------------------------------------
@@ -658,7 +723,7 @@
               end
 
             8'h22: // Wait
-              begin : Wait
+              begin : OpCode22
                 reg NoTimeOut;
                 Count = Get16bit(i); // Timeout in ns
                 if ( Count==0 )
@@ -689,6 +754,34 @@
                     $display( "...Done waiting (time remaining = %0d ns)!", 
Count );
               end
 
+            8'h23: // Inject bit error in Tx packet
+              begin
+                $display( "Injecting a single bit-error in Tx packet..." );
+                InjectError = 1;
+              end
+
+            8'h24: // Store internally generated PAUSE frame in Rx expect queue
+              begin
+                Count = Get16bit(i); // Timeout in ns
+                $display( "Generating PAUSE frame (tick=%0d) on Rx expect 
queue", Count );
+                RxExpectPacketCount = RxExpectPacketCount + 1;
+                FIFO_Wr( { 1'b1, 1'b0, 2'b00, 32'h0180c200 } );
+                FIFO_Wr( { 1'b0, 1'b0, 2'b00, 16'h0001, 16'h0000 } );
+                FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
+                FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h88080001 } );
+                FIFO_Wr( { 1'b0, 1'b0, 2'b00, Count, 16'h0000 } );
+                FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
+                FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
+                FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
+                FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
+                FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
+                FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
+                FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
+                FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
+                FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
+                FIFO_Wr( { 1'b0, 1'b1, 2'b00, 32'h00000000 } );
+              end
+
             8'hff: // Halt
               begin
                 $display( "HALT" );
@@ -790,7 +883,7 @@
       RxByteCount = 0;
 
       for ( i=0; i<`TXDATALEN; i=i+1 )
-        TxData[i] = 8'h00;
+        TxData[i] = (i & 8'hff);
 
       // Fill script memory with HALTs
       for ( i=0; i<`SCRIPTLEN; i=i+1 )
@@ -812,7 +905,7 @@
       ExecuteScript;
     end
 
-   initial $dumpfile("tb_top.vcd");
-   initial $dumpvars(0,tb_top);
+    initial $dumpfile("tb_top.vcd");
+    initial $dumpvars(0,tb_top);
 
 endmodule

Modified: gnuradio/branches/developers/matt/u2f/eth/bench/verilog/test.scr
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/bench/verilog/test.scr    
2007-08-23 18:53:51 UTC (rev 6171)
+++ gnuradio/branches/developers/matt/u2f/eth/bench/verilog/test.scr    
2007-08-23 22:46:35 UTC (rev 6172)
@@ -1,90 +1,23 @@
-// Read from register 0 and expect 9 - just a test...
-03 00 00 00 09 ff ff
+// This tests just runs trough a couple of different packet lengths
 
+// Read from register 24 to confirm that Rx CRC check is enabled
+03 00 18 00 01 ff ff
+
 // Set speed to 1000 Mbps
 01 00 22 00 04
 
-// Write MAC address 12 35 56 78 9A BC to Rx Address buffer
-01 00 10 00 00
-01 00 0f 00 12
-01 00 11 00 01
-01 00 11 00 00
-01 00 10 00 01
-01 00 0f 00 34
-01 00 11 00 01
-01 00 11 00 00
-01 00 10 00 02
-01 00 0f 00 56
-01 00 11 00 01
-01 00 11 00 00
-01 00 10 00 03
-01 00 0f 00 78
-01 00 11 00 01
-01 00 11 00 00
-01 00 10 00 04
-01 00 0f 00 9A
-01 00 11 00 01
-01 00 11 00 00
-01 00 10 00 05
-01 00 0f 00 BC
-01 00 11 00 01
-01 00 11 00 00
-
-// Write 1 to register 14, MAC_rx_add_chk_e
-01 00 0e 00 01
-
 // Setup Tx and Rx MAC addresses and type field to "IP"
 // Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
 10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
 
-// Transmit a 60-byte frame 1 time - and expect it to be received again!
-20 00 3C 00 01
-// Transmit a 61-byte frame 1 time - and expect it to be received again!
-20 00 3D 00 01
-// Transmit a 62-byte frame 1 time - and expect it to be received again!
-20 00 3E 00 01
-// Transmit a 63-byte frame 1 time - and expect it to be received again!
-20 00 3F 00 01
-// Transmit a 64-byte frame 1 time - and expect it to be received again!
-20 00 40 00 01
+// Transmit a 320-byte frame 1 time - and expect it to be received again!
+20 01 40 00 01
 
-// Transmit a 2048-byte frame 7 times - and expect it to be received again!
-//20 08 00 00 07
+// Transmit a 80-byte frame 1 time - and expect it to be received again!
+20 00 50 00 01
 
-// Transmit a 60-byte frame 1 time - and expect it to be received again!
-20 00 3C 00 01
-// Transmit a 1500-byte frame 1 time - and expect it to be received again!
-20 05 DC 00 01
-// Transmit a 500-byte frame 1 time - and expect it to be received again!
-//20 01 F4 00 01
-// Transmit a 1510-byte frame 1 time - and expect it to be received again!
-//20 05 E6 00 01
-
-20 00 40 00 01
-
 // Wait (indefinitely) for missing Rx packets
 22 00 00 
 
 // Halt
 FF
-
-// Change Tx MAC to something different - we won't receive frames with this ID
-10 00 00 00 06 11 22 33 44 55 66
-
-// Transmit a 60 byte frame 3 times - but don't expect it to be received!
-20 00 3C 00 05
-
-22 01 00
-
-//
-//// Change Tx MAC back to 12 34 56 78 9A BC
-//10 00 00 00 06 12 34 56 78 9A BC
-//
-//// Transmit a 60 byte frame 3 times - and expect it to be received again!
-//20 00 3C 00 05
-//
-
-// Some trailing NOPs...
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 

Modified: gnuradio/branches/developers/matt/u2f/eth/mac_txfifo_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/mac_txfifo_int.v  2007-08-23 
18:53:51 UTC (rev 6171)
+++ gnuradio/branches/developers/matt/u2f/eth/mac_txfifo_int.v  2007-08-23 
22:46:35 UTC (rev 6172)
@@ -20,5 +20,6 @@
    assign Tx_mac_eop = rd_empty_i;
    assign Tx_mac_BE = 0;
    
+   
+endmodule // mac_txfifo_int
 
-endmodule // mac_txfifo_int

Modified: gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/Phy_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/Phy_int.v     
2007-08-23 18:53:51 UTC (rev 6171)
+++ gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/Phy_int.v     
2007-08-23 22:46:35 UTC (rev 6172)
@@ -54,174 +54,187 @@
 // 
 
 module Phy_int (
-Reset               ,
-MAC_rx_clk          ,
-MAC_tx_clk          ,
-//Rx interface      ,
-MCrs_dv             ,
-MRxD                ,
-MRxErr              ,
-//Tx interface      ,
-MTxD                ,
-MTxEn               ,
-MCRS                ,
-//Phy interface     ,
-Tx_er               ,
-Tx_en               ,
-Txd                 ,
-Rx_er               ,
-Rx_dv               ,
-Rxd                 ,
-Crs                 ,
-Col                 ,
-//host interface    ,
-Line_loop_en        ,
-Speed               
+  Reset,
+  MAC_rx_clk,
+  MAC_tx_clk,
 
+  // Rx interface
+  MCrs_dv,
+  MRxD,
+  MRxErr,
+
+  // Tx interface
+  MTxD,
+  MTxEn,
+  MCRS,
+
+  // PHY interface
+  Tx_er,
+  Tx_en,
+  Txd,
+  Rx_er,
+  Rx_dv,
+  Rxd,
+  Crs,
+  Col,
+
+  // Host interface
+  Line_loop_en,
+  Speed
 );
-input           Reset               ;
-input           MAC_rx_clk          ;
-input           MAC_tx_clk          ;
-                //Rx interface
-output          MCrs_dv             ;       
-output  [7:0]   MRxD                ;       
-output          MRxErr              ;       
-                //Tx interface
-input   [7:0]   MTxD                ;
-input           MTxEn               ;   
-output          MCRS                ;
-                //Phy interface
-output          Tx_er               ;
-output          Tx_en               ;
-output  [7:0]   Txd                 ;
-input           Rx_er               ;
-input           Rx_dv               ;
-input   [7:0]   Rxd                 ;
-input           Crs                 ;
-input           Col                 ;
-                //host interface
-input           Line_loop_en        ;
-input   [2:0]   Speed               ;
-//******************************************************************************
-//internal signals                                                             
 
-//******************************************************************************
-reg     [7:0]   MTxD_dl1            ;
-reg             MTxEn_dl1           ;
-reg             Tx_odd_data_ptr     ;  
-reg             Rx_odd_data_ptr     ;
-reg             Tx_en               ;
-reg     [7:0]   Txd                 ;
-reg             MCrs_dv             ;
-reg     [7:0]   MRxD                ;
-reg             Rx_er_dl1           ;
-reg             Rx_dv_dl1           ;
-reg             Rx_dv_dl2           ;
-reg     [7:0]   Rxd_dl1             ;
-reg     [7:0]   Rxd_dl2             ;
-reg             Crs_dl1             ;
-reg             Col_dl1             ;
-//******************************************************************************
-//Tx control                                                              
-//******************************************************************************
-//reg boundery signals
-always @ (posedge MAC_tx_clk or posedge Reset)
-    if (Reset)
-        begin
-        MTxD_dl1            <=0;
-        MTxEn_dl1           <=0;
-        end  
+
+  input        Reset;
+  input        MAC_rx_clk;
+  input        MAC_tx_clk;
+
+  // Rx interface
+  output       MCrs_dv;
+  output [7:0] MRxD;
+  output       MRxErr;
+
+  // Tx interface
+  input [7:0]  MTxD;
+  input        MTxEn;
+  output       MCRS;
+
+  // PHY interface
+  output       Tx_er;
+  output       Tx_en;
+  output [7:0] Txd;
+  input        Rx_er;
+  input        Rx_dv;
+  input [7:0]  Rxd;
+  input        Crs;
+  input        Col;
+
+  // Host interface
+  input        Line_loop_en;
+  input [2:0]  Speed;
+
+  //-------------------------------------------------------------------------
+  // Local declarations
+  //-------------------------------------------------------------------------
+
+  reg [7:0] MTxD_dl1;
+  reg       MTxEn_dl1;
+  reg       Tx_odd_data_ptr;
+  reg       Rx_odd_data_ptr;
+  reg       Tx_en;
+  reg [7:0] Txd;
+  reg       MCrs_dv;
+  reg [7:0] MRxD;
+  reg       Rx_er_dl1;
+  reg       Rx_dv_dl1;
+  reg       Rx_dv_dl2;
+  reg [7:0] Rxd_dl1;
+  reg [7:0] Rxd_dl2;
+  reg       Crs_dl1;
+  reg       Col_dl1;
+
+  //-------------------------------------------------------------------------
+  // Tx control
+  //-------------------------------------------------------------------------
+
+  // Reg boundary signals
+  always @( posedge MAC_tx_clk or posedge Reset )
+    if ( Reset )
+      begin
+        MTxD_dl1  <= 0;
+        MTxEn_dl1 <= 0;
+      end  
     else
-        begin
-        MTxD_dl1            <=MTxD  ;
-        MTxEn_dl1           <=MTxEn ;
-        end 
+      begin
+        MTxD_dl1  <= MTxD;
+        MTxEn_dl1 <= MTxEn;
+      end 
      
-always @ (posedge MAC_tx_clk or posedge Reset)
-    if (Reset)   
-        Tx_odd_data_ptr     <=0;
-    else if (!MTxD_dl1)
-        Tx_odd_data_ptr     <=0;
+  always @( posedge MAC_tx_clk or posedge Reset )
+    if ( Reset )   
+      Tx_odd_data_ptr <= 0;
+    else if ( !MTxD_dl1 )
+      Tx_odd_data_ptr <= 0;
     else 
-        Tx_odd_data_ptr     <=!Tx_odd_data_ptr;
+      Tx_odd_data_ptr <= !Tx_odd_data_ptr;
         
 
-always @ (posedge MAC_tx_clk or posedge Reset)
-    if (Reset)  
-        Txd                 <=0;
-    else if(Speed[2]&&MTxEn_dl1)
-        Txd                 <=MTxD_dl1;
-    else if(MTxEn_dl1&&!Tx_odd_data_ptr)
-        Txd                 <={4'b0,MTxD_dl1[3:0]};
-    else if(MTxEn_dl1&&Tx_odd_data_ptr)
-        Txd                 <={4'b0,MTxD_dl1[7:4]};
+  always @( posedge MAC_tx_clk or posedge Reset )
+    if ( Reset )
+      Txd <= 0;
+    else if ( Speed[2] && MTxEn_dl1 )
+      Txd <= MTxD_dl1;
+    else if ( MTxEn_dl1 && !Tx_odd_data_ptr )
+      Txd <= { 4'b0, MTxD_dl1[3:0] };
+    else if ( MTxEn_dl1 &&  Tx_odd_data_ptr )
+      Txd <= { 4'b0, MTxD_dl1[7:4] };
     else
-        Txd                 <=0;
+      Txd <=0;
 
-always @ (posedge MAC_tx_clk or posedge Reset)
-    if (Reset)  
-        Tx_en               <=0;
-    else if(MTxEn_dl1)
-        Tx_en               <=1;    
+  always @( posedge MAC_tx_clk or posedge Reset )
+    if ( Reset )
+      Tx_en <= 0;
+    else if ( MTxEn_dl1 )
+      Tx_en <= 1;    
     else
-        Tx_en               <=0;
+      Tx_en <= 0;
 
-assign Tx_er=0;
+  assign Tx_er = 0;
 
-//******************************************************************************
-//Rx control                                                              
-//******************************************************************************
-//reg boundery signals
-always @ (posedge MAC_rx_clk or posedge Reset)
-    if (Reset)  
-        begin
-        Rx_er_dl1           <=0;
-        Rx_dv_dl1           <=0;
-        Rx_dv_dl2           <=0 ;
-        Rxd_dl1             <=0;
-        Rxd_dl2             <=0;
-        Crs_dl1             <=0;
-        Col_dl1             <=0;
-        end
+  //-------------------------------------------------------------------------
+  // Rx control
+  //-------------------------------------------------------------------------
+
+  // Reg boundery signals
+  always @( posedge MAC_rx_clk or posedge Reset )
+    if ( Reset )
+      begin
+        Rx_er_dl1 <= 0;
+        Rx_dv_dl1 <= 0;
+        Rx_dv_dl2 <= 0;
+        Rxd_dl1   <= 0;
+        Rxd_dl2   <= 0;
+        Crs_dl1   <= 0;
+        Col_dl1   <= 0;
+      end
     else
-        begin
-        Rx_er_dl1           <=Rx_er     ;
-        Rx_dv_dl1           <=Rx_dv     ;
-        Rx_dv_dl2           <=Rx_dv_dl1 ;
-        Rxd_dl1             <=Rxd       ;
-        Rxd_dl2             <=Rxd_dl1   ;
-        Crs_dl1             <=Crs       ;
-        Col_dl1             <=Col       ;
-        end     
+      begin
+        Rx_er_dl1 <= Rx_er;
+        Rx_dv_dl1 <= Rx_dv;
+        Rx_dv_dl2 <= Rx_dv_dl1;
+        Rxd_dl1   <= Rxd;
+        Rxd_dl2   <= Rxd_dl1;
+        Crs_dl1   <= Crs;
+        Col_dl1   <= Col;
+      end
 
-assign MRxErr   =Rx_er_dl1      ;
-assign MCRS     =Crs_dl1        ;
+  assign MRxErr = Rx_er_dl1;
+  assign MCRS   = Crs_dl1;
 
-always @ (posedge MAC_rx_clk or posedge Reset)
-    if (Reset)  
-        MCrs_dv         <=0;
-    else if(Line_loop_en)
-        MCrs_dv         <=Tx_en;
-    else if(Rx_dv_dl2)
-        MCrs_dv         <=1;
+  always @( posedge MAC_rx_clk or posedge Reset )
+    if ( Reset )
+      MCrs_dv <= 0;
+    else if ( Line_loop_en )
+      MCrs_dv <= Tx_en;
+    else if( Rx_dv_dl2 )
+      MCrs_dv <= 1;
     else
-        MCrs_dv         <=0;
+      MCrs_dv <= 0;
 
-always @ (posedge MAC_rx_clk or posedge Reset)
-    if (Reset)   
-        Rx_odd_data_ptr     <=0;
-    else if (!Rx_dv_dl1)
-        Rx_odd_data_ptr     <=0;
+  always @ ( posedge MAC_rx_clk or posedge Reset )
+    if ( Reset )
+      Rx_odd_data_ptr <= 0;
+    else if ( !Rx_dv_dl1 )
+      Rx_odd_data_ptr <= 0;
     else 
-        Rx_odd_data_ptr     <=!Rx_odd_data_ptr;
-        
-always @ (posedge MAC_rx_clk or posedge Reset)
-    if (Reset)  
-        MRxD            <=0;
-    else if(Line_loop_en)
-        MRxD            <=Txd;
-    else if(Speed[2]&&Rx_dv_dl2)
-        MRxD            <=Rxd_dl2;
-    else if(Rx_dv_dl1&&Rx_odd_data_ptr)
-        MRxD            <={Rxd_dl1[3:0],Rxd_dl2[3:0]};
-    
-endmodule           
\ No newline at end of file
+      Rx_odd_data_ptr <= !Rx_odd_data_ptr;
+
+  always @ ( posedge MAC_rx_clk or posedge Reset )
+    if ( Reset )  
+      MRxD <= 0;
+    else if( Line_loop_en )
+      MRxD <= Txd;
+    else if( Speed[2] && Rx_dv_dl2 )
+      MRxD <= Rxd_dl2;
+    else if( Rx_dv_dl1 && Rx_odd_data_ptr )
+      MRxD <={ Rxd_dl1[3:0], Rxd_dl2[3:0] };
+
+endmodule           

Deleted: gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/RMON/RMON_CTRL.v

Added: gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/RMON/RMON_ctrl.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/RMON/RMON_ctrl.v      
                        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/RMON/RMON_ctrl.v      
2007-08-23 22:46:35 UTC (rev 6172)
@@ -0,0 +1,290 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  RMON_ctrl.v                                                 ////
+////                                                              ////
+////  This file is part of the Ethernet IP core project           ////
+////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Jon Gao (address@hidden)                            ////
+////                                                              ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2001 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//                                                                    
+// CVS Revision History                                               
+//                                                                    
+// $Log: RMON_ctrl.v,v $
+// Revision 1.4  2006/06/25 04:58:57  maverickist
+// no message
+//
+// Revision 1.3  2006/01/19 14:07:55  maverickist
+// verification is complete.
+//
+// Revision 1.2  2005/12/16 06:44:19  Administrator
+// replaced tab with space.
+// passed 9.6k length frame test.
+//
+// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
+// no message
+//  
+module RMON_ctrl (
+Clk             ,      
+Reset           ,      
+//RMON_ctrl        
+Reg_apply_0     ,      
+Reg_addr_0      ,      
+Reg_data_0      ,      
+Reg_next_0      ,      
+Reg_apply_1     ,      
+Reg_addr_1      ,      
+Reg_data_1      ,      
+Reg_next_1      ,      
+//dual-port ram
+Addra               ,  
+Dina                ,  
+Douta               ,  
+Wea                 ,  
+//CPU                  
+CPU_rd_addr     ,  
+CPU_rd_apply        ,  
+CPU_rd_grant        ,
+CPU_rd_dout
+
+);
+input           Clk             ;
+input           Reset           ;
+                //RMON_ctrl
+input           Reg_apply_0     ;
+input   [4:0]   Reg_addr_0      ;
+input   [15:0]  Reg_data_0      ;
+output          Reg_next_0      ;
+input           Reg_apply_1     ;
+input   [4:0]   Reg_addr_1      ;
+input   [15:0]  Reg_data_1      ;
+output          Reg_next_1      ;
+                //dual-port ram 
+                //port-a for Rmon  
+output  [5:0]   Addra               ;
+output  [31:0]  Dina                ;
+input   [31:0]  Douta               ;
+output          Wea                 ;
+                //CPU
+input   [5:0]   CPU_rd_addr         ;
+input           CPU_rd_apply        ;
+output          CPU_rd_grant        ;
+output  [31:0]  CPU_rd_dout         ;
+
+
+
+
+//******************************************************************************
+//internal signals                                                             
 
+//******************************************************************************
+
+parameter       StateCPU        =4'd00;
+parameter       StateMAC0       =4'd01;
+parameter       StateMAC1       =4'd02;
+
+
+reg [3:0]       CurrentState /* synthesys syn_keep=1 */;
+reg [3:0]       NextState;
+reg [3:0]       CurrentState_reg;
+
+reg [4:0]       StepCounter;
+reg [31:0]      DoutaReg;
+reg [5:0]       Addra               ;
+reg [31:0]      Dina;
+reg             Reg_next_0      ;
+reg             Reg_next_1      ;
+reg             Write;
+reg             Read;
+reg             Pipeline;
+reg [31:0]      CPU_rd_dout         ;
+reg             CPU_rd_apply_reg    ;
+//******************************************************************************
+//State Machine                                                            
+//******************************************************************************
+
+always @(posedge Clk or posedge Reset)
+    if (Reset)
+        CurrentState    <=StateMAC0;
+    else
+        CurrentState    <=NextState;
+        
+always @(posedge Clk or posedge Reset)
+    if (Reset)  
+        CurrentState_reg    <=StateMAC0;
+    else if(CurrentState!=StateCPU)
+        CurrentState_reg    <=CurrentState;
+                
+always @(CurrentState or CPU_rd_apply_reg or Reg_apply_0 or CurrentState_reg
+                                       or Reg_apply_1   
+                                       or StepCounter
+                                       )
+    case(CurrentState)
+        StateMAC0:
+            if(!Reg_apply_0&&CPU_rd_apply_reg)
+                NextState   =StateCPU;
+            else if(!Reg_apply_0)
+                NextState   =StateMAC1;
+            else
+                NextState   =CurrentState;
+        StateMAC1:
+            if(!Reg_apply_1&&CPU_rd_apply_reg)
+                NextState   =StateCPU;
+            else if(!Reg_apply_1)
+                NextState   =StateMAC0;
+            else
+                NextState   =CurrentState;
+        StateCPU:
+            if (StepCounter==3)
+                case (CurrentState_reg)
+                    StateMAC0   :NextState  =StateMAC0 ;
+                    StateMAC1   :NextState  =StateMAC1 ;
+                    default     :NextState  =StateMAC0;
+                endcase
+            else
+                NextState   =CurrentState;
+            
+        default:
+                NextState   =StateMAC0;
+    endcase
+                
+
+
+always @(posedge Clk or posedge Reset)
+    if (Reset)
+        StepCounter     <=0;
+    else if(NextState!=CurrentState)
+        StepCounter     <=0;
+    else if (StepCounter!=4'hf)
+        StepCounter     <=StepCounter + 1;
+
+//******************************************************************************
+//temp signals                                                            
+//******************************************************************************
+always @(StepCounter)
+    if( StepCounter==1||StepCounter==4||
+        StepCounter==7||StepCounter==10)
+        Read    =1;
+    else
+        Read    =0;
+
+always @(StepCounter or CurrentState)
+    if( StepCounter==2||StepCounter==5||
+        StepCounter==8||StepCounter==11)
+        Pipeline    =1;
+    else
+        Pipeline    =0;
+                
+always @(StepCounter or CurrentState)
+    if( StepCounter==3||StepCounter==6||
+        StepCounter==9||StepCounter==12)
+        Write   =1;
+    else
+        Write   =0;
+        
+always @(posedge Clk or posedge Reset)
+    if (Reset)
+        DoutaReg        <=0;
+    else if (Read)
+        DoutaReg        <=Douta;
+        
+        
+//******************************************************************************
+//gen output signals                                                        
+//******************************************************************************
    
+//Addra 
+always @(*)
+    case(CurrentState)
+        StateMAC0 :     Addra={1'd0 ,Reg_addr_0 };
+        StateMAC1 :     Addra={1'd1 ,Reg_addr_1 };
+        StateCPU:       Addra=CPU_rd_addr;
+        default:        Addra=0;
+        endcase
+    
+//Dina
+always @(posedge Clk or posedge Reset)
+    if (Reset)
+        Dina    <=0;
+    else 
+        case(CurrentState)
+            StateMAC0 :     Dina<=Douta+Reg_data_0 ;
+            StateMAC1 :     Dina<=Douta+Reg_data_1 ;
+            StateCPU:       Dina<=0;
+            default:        Dina<=0;
+        endcase
+    
+assign  Wea     =Write;
+//Reg_next
+always @(CurrentState or Pipeline)
+    if(CurrentState==StateMAC0)
+        Reg_next_0  =Pipeline;
+    else
+        Reg_next_0  =0;
+    
+always @(CurrentState or Pipeline)
+    if(CurrentState==StateMAC1)
+        Reg_next_1  =Pipeline;
+    else
+        Reg_next_1  =0;     
+
+
+//CPU_rd_grant   
+reg     CPU_rd_apply_dl1;
+reg     CPU_rd_apply_dl2;
+//rising edge
+always @ (posedge Clk or posedge Reset)
+    if (Reset)
+        begin
+        CPU_rd_apply_dl1        <=0;
+        CPU_rd_apply_dl2        <=0;
+        end
+    else
+        begin
+        CPU_rd_apply_dl1        <=CPU_rd_apply;
+        CPU_rd_apply_dl2        <=CPU_rd_apply_dl1;
+        end     
+
+always @ (posedge Clk or posedge Reset)
+    if (Reset)
+        CPU_rd_apply_reg    <=0;
+    else if (CPU_rd_apply_dl1&!CPU_rd_apply_dl2)
+        CPU_rd_apply_reg    <=1;
+    else if (CurrentState==StateCPU&&Write)
+        CPU_rd_apply_reg    <=0;
+
+assign CPU_rd_grant =!CPU_rd_apply_reg;
+
+always @ (posedge Clk or posedge Reset)
+    if (Reset)
+        CPU_rd_dout     <=0;
+    else if (Pipeline&&CurrentState==StateCPU)
+        CPU_rd_dout     <=Douta;        
+
+endmodule           

Modified: gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/RMON.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/RMON.v        
2007-08-23 18:53:51 UTC (rev 6171)
+++ gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/RMON.v        
2007-08-23 22:46:35 UTC (rev 6172)
@@ -144,10 +144,10 @@
  //CPU                  (//CPU                       ),                        
         
 .Reg_drop_apply         (                           ));
 
-RMON_CTRL U_RMON_CTRL(
+RMON_ctrl U_RMON_ctrl(
 .Clk                    (Clk                        ),        
 .Reset                  (Reset                      ), 
- //RMON_CTRL            (//RMON_CTRL                ),  
+ //RMON_ctrl            (//RMON_ctrl                ),  
 .Reg_apply_0            (Reg_apply_0                ),         
 .Reg_addr_0             (Reg_addr_0                 ), 
 .Reg_data_0             (Reg_data_0                 ), 

Modified: gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/Reg_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/Reg_int.v     
2007-08-23 18:53:51 UTC (rev 6171)
+++ gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/Reg_int.v     
2007-08-23 22:46:35 UTC (rev 6172)
@@ -176,7 +176,7 @@
   RegCPUData U_0_021( RX_APPEND_CRC_int            , 7'd021, 16'h0000, RST_I, 
CLK_I, Wr, ADR_I, DAT_I );
   RegCPUData U_0_022( Rx_Hwmark_int                , 7'd022, 16'h001a, RST_I, 
CLK_I, Wr, ADR_I, DAT_I );
   RegCPUData U_0_023( Rx_Lwmark_int                , 7'd023, 16'h0010, RST_I, 
CLK_I, Wr, ADR_I, DAT_I );
-  RegCPUData U_0_024( CRC_chk_en_int               , 7'd024, 16'h0000, RST_I, 
CLK_I, Wr, ADR_I, DAT_I );
+  RegCPUData U_0_024( CRC_chk_en_int               , 7'd024, 16'h0001, RST_I, 
CLK_I, Wr, ADR_I, DAT_I );
   RegCPUData U_0_025( RX_IFG_SET_int               , 7'd025, 16'h000c, RST_I, 
CLK_I, Wr, ADR_I, DAT_I );
   RegCPUData U_0_026( RX_MAX_LENGTH_int            , 7'd026, 16'h2710, RST_I, 
CLK_I, Wr, ADR_I, DAT_I );
   RegCPUData U_0_027( RX_MIN_LENGTH_int            , 7'd027, 16'h0040, RST_I, 
CLK_I, Wr, ADR_I, DAT_I );

Modified: 
gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/TECH/xilinx/RAMB16_S36_S36.v
===================================================================
--- 
gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/TECH/xilinx/RAMB16_S36_S36.v
  2007-08-23 18:53:51 UTC (rev 6171)
+++ 
gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/TECH/xilinx/RAMB16_S36_S36.v
  2007-08-23 22:46:35 UTC (rev 6172)
@@ -1555,10 +1555,10 @@
            deassign dopb_out;
        end
 
-    initial begin
+    initial begin : initialize_mems
 
+`ifdef UNDEFINED
        for (count = 0; count < 8; count = count + 1) begin
-`ifdef UNDEFINED
            mem[count]          = INIT_00[(count * 32) +: 32];
            mem[8 * 1 + count]  = INIT_01[(count * 32) +: 32];
            mem[8 * 2 + count]  = INIT_02[(count * 32) +: 32];
@@ -1623,12 +1623,20 @@
            mem[8 * 61 + count] = INIT_3D[(count * 32) +: 32];
            mem[8 * 62 + count] = INIT_3E[(count * 32) +: 32];
            mem[8 * 63 + count] = INIT_3F[(count * 32) +: 32];
-`endif
        end
+`else
+      integer i;
+      for (i = 0; i < 512; i = i + 1)
+        begin
+          mem[i] = 0;
+          memp[i] = 0;
+        end
 
+`endif
+
 // initiate parity start
+`ifdef UNDEFINED
        for (countp = 0; countp < 64; countp = countp + 1) begin
-`ifdef UNDEFINED
            memp[countp]          = INITP_00[(countp * 4) +: 4];
            memp[64 * 1 + countp] = INITP_01[(countp * 4) +: 4];
            memp[64 * 2 + countp] = INITP_02[(countp * 4) +: 4];
@@ -1637,8 +1645,8 @@
            memp[64 * 5 + countp] = INITP_05[(countp * 4) +: 4];
            memp[64 * 6 + countp] = INITP_06[(countp * 4) +: 4];
            memp[64 * 7 + countp] = INITP_07[(countp * 4) +: 4];
+       end
 `endif
-       end
 // initiate parity end
        
        change_clka <= 0;





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