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[Commit-gnuradio] r7447 - usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx
From: |
matt |
Subject: |
[Commit-gnuradio] r7447 - usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx |
Date: |
Tue, 15 Jan 2008 22:35:20 -0700 (MST) |
Author: matt
Date: 2008-01-15 22:35:20 -0700 (Tue, 15 Jan 2008)
New Revision: 7447
Modified:
usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
Log:
fixed annoying speling erors
Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2008-01-16 03:11:09 UTC
(rev 7446)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2008-01-16 05:35:20 UTC
(rev 7447)
@@ -133,10 +133,10 @@
reg Wr_en;
reg Wr_en_tmp;
reg Wr_en_ptr;
- wire [RX_FF_DEPTH-1:0] Add_wr_pluse;
- wire [RX_FF_DEPTH-1:0] Add_wr_pluse4;
- wire [RX_FF_DEPTH-1:0] Add_wr_pluse3;
- wire [RX_FF_DEPTH-1:0] Add_wr_pluse2;
+ wire [RX_FF_DEPTH-1:0] Add_wr_plus4;
+ wire [RX_FF_DEPTH-1:0] Add_wr_plus3;
+ wire [RX_FF_DEPTH-1:0] Add_wr_plus2;
+ wire [RX_FF_DEPTH-1:0] Add_wr_plus1;
reg Full;
reg Almost_full;
@@ -311,15 +311,15 @@
else
Add_rd_ungray <= Add_rd_ungray_next;
- assign Add_wr_pluse = Add_wr + 1;
- assign Add_wr_pluse2 = Add_wr + 2;
- assign Add_wr_pluse3 = Add_wr + 3;
- assign Add_wr_pluse4 = Add_wr + 4;
+ assign Add_wr_plus1 = Add_wr + 1;
+ assign Add_wr_plus2 = Add_wr + 2;
+ assign Add_wr_plus3 = Add_wr + 3;
+ assign Add_wr_plus4 = Add_wr + 4;
always @ ( posedge Clk_MAC or posedge Reset )
if ( Reset )
Full <=0;
- else if ( Add_wr_pluse==Add_rd_ungray )
+ else if ( Add_wr_plus1==Add_rd_ungray )
Full <= 1;
else
Full <= 0;
@@ -327,10 +327,10 @@
always @ ( posedge Clk_MAC or posedge Reset )
if ( Reset )
Almost_full <= 0;
- else if ( (Add_wr_pluse4==Add_rd_ungray) ||
- (Add_wr_pluse3==Add_rd_ungray) ||
- (Add_wr_pluse2==Add_rd_ungray) ||
- (Add_wr_pluse ==Add_rd_ungray)
+ else if ( (Add_wr_plus4==Add_rd_ungray) ||
+ (Add_wr_plus3==Add_rd_ungray) ||
+ (Add_wr_plus2==Add_rd_ungray) ||
+ (Add_wr_plus1==Add_rd_ungray)
)
Almost_full <= 1;
else
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