[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Commit-gnuradio] r7830 - usrp2/trunk/fpga/top/u2_basic
From: |
matt |
Subject: |
[Commit-gnuradio] r7830 - usrp2/trunk/fpga/top/u2_basic |
Date: |
Sun, 24 Feb 2008 17:47:58 -0700 (MST) |
Author: matt
Date: 2008-02-24 17:47:58 -0700 (Sun, 24 Feb 2008)
New Revision: 7830
Modified:
usrp2/trunk/fpga/top/u2_basic/u2_basic.v
Log:
debug ports
Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v 2008-02-25 00:47:31 UTC (rev
7829)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v 2008-02-25 00:47:58 UTC (rev
7830)
@@ -605,21 +605,23 @@
wire [31:0] debug_eth =
{{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write},
- {2'b0,iwb_adr[13:0]},
+ {8'd0},
+ {8'd0},
{GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full}
};
/*
assign debug_serdes0 = { { rd0_dat },
{ ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop,
rd0_eop, rd0_read, rd0_error, rd0_done },
{ ser_t[15:8] },
{ ser_t[7:0] } };
- */
+
assign debug_serdes1 = {
{uart_tx_o,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write},
{ 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb,
ser_enable, ser_prbsen, ser_loopen, ser_rx_en },
{ ser_r[15:8] },
{ ser_r[7:0] } };
+ */
// Choose actual debug buses
- assign debug = debug_serdes0;
+ assign debug = debug_mac0;
assign debug_clk[0] = wb_clk;
assign debug_clk[1] = dsp_clk;
assign debug_gpio_0 = 32'd0; // Not used b/c of ATR
@@ -628,7 +630,8 @@
3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error,
debug_txc[15:0]};
assign debug_gpio_1 = debug_rx;
-*/
assign debug_gpio_1 = debug_serdes1;
-
+ */
+ assign debug_gpio_1 = debug_eth;
+
endmodule // u2_basic
[Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Commit-gnuradio] r7830 - usrp2/trunk/fpga/top/u2_basic,
matt <=