[Commit-gnuradio] r7952 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2008-03-06 14:53:18 -0700 (Thu, 06 Mar 2008)
New Revision: 7952

Added:
   usrp2/trunk/fpga/sdr_lib/add2_and_round_reg.v
   usrp2/trunk/fpga/sdr_lib/clip.v
   usrp2/trunk/fpga/sdr_lib/clip_reg.v
   usrp2/trunk/fpga/sdr_lib/round_reg.v
Modified:
   usrp2/trunk/fpga/sdr_lib/round.v
Log:
following the don't repeat yourself principle, these are abstracted out


Added: usrp2/trunk/fpga/sdr_lib/add2_and_round_reg.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/add2_and_round_reg.v                               
(rev 0)
+++ usrp2/trunk/fpga/sdr_lib/add2_and_round_reg.v       2008-03-06 21:53:18 UTC 
(rev 7952)
@@ -0,0 +1,16 @@
+
+module add2_and_round_reg
+  #(parameter WIDTH=16)
+    (input clk,
+     input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output reg [WIDTH-1:0] sum);
+
+   wire [WIDTH-1:0] sum_int;
+   
+   add2_and_round #(.WIDTH(WIDTH)) add2_n_rnd 
(.in1(in1),.in2(in2),.sum(sum_int));
+
+   always @(posedge clk)
+     sum <= sum_int;
+   
+endmodule // add2_and_round_reg

Added: usrp2/trunk/fpga/sdr_lib/clip.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/clip.v                             (rev 0)
+++ usrp2/trunk/fpga/sdr_lib/clip.v     2008-03-06 21:53:18 UTC (rev 7952)
@@ -0,0 +1,36 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2008 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Clipping "macro", keeps the bottom bits
+
+module clip
+  #(parameter bits_in=0,
+    parameter bits_out=0)
+    (input [bits_in-1:0] in,
+     output [bits_out-1:0] out);
+   
+   wire                   overflow = |in[bits_in-1:bits_out-1] & 
~(&in[bits_in-1:bits_out-1]);   
+   assign                 out = overflow ? 
+                          (in[bits_in-1] ? {1'b1,{(bits_out-1){1'b0}}} : 
{1'b0,{(bits_out-1){1'b1}}}) :
+                          in[bits_out-1:0];
+   
+endmodule // clip
+

Added: usrp2/trunk/fpga/sdr_lib/clip_reg.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/clip_reg.v                         (rev 0)
+++ usrp2/trunk/fpga/sdr_lib/clip_reg.v 2008-03-06 21:53:18 UTC (rev 7952)
@@ -0,0 +1,39 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2008 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Clipping "macro", keeps the bottom bits
+
+module clip_reg
+  #(parameter bits_in=0,
+    parameter bits_out=0)
+    (input clk,
+     input [bits_in-1:0] in,
+     output reg [bits_out-1:0] out);
+   
+   wire [bits_out-1:0] temp;
+
+   clip #(.bits_in(bits_in),.bits_out(bits_out)) clip (.in(in),.out(out));
+   always @(posedge clk)
+     out <= temp;
+
+   
+endmodule // clip_reg
+

Modified: usrp2/trunk/fpga/sdr_lib/round.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/round.v    2008-03-06 06:32:18 UTC (rev 7951)
+++ usrp2/trunk/fpga/sdr_lib/round.v    2008-03-06 21:53:18 UTC (rev 7952)
@@ -20,7 +20,7 @@
 //
 
 // Rounding "macro"
-// Keeps the topmost bits, does proper 2s comp rounding
+// Keeps the topmost bits, does proper 2s comp rounding - round to zero
 
 module round
   #(parameter bits_in=0,

Added: usrp2/trunk/fpga/sdr_lib/round_reg.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/round_reg.v                                (rev 0)
+++ usrp2/trunk/fpga/sdr_lib/round_reg.v        2008-03-06 21:53:18 UTC (rev 
7952)
@@ -0,0 +1,39 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2008 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Rounding "macro"
+// Keeps the topmost bits, does proper 2s comp rounding (round-to-zero)
+
+module round_reg
+  #(parameter bits_in=0,
+    parameter bits_out=0)
+    (input clk,
+     input [bits_in-1:0] in,
+     output reg [bits_out-1:0] out);
+
+   wire [bits_out-1:0] temp;
+
+   round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp));
+   
+   always @(posedge clk)
+     out <= temp;
+   
+endmodule // round