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[Commit-gnuradio] r8234 - usrp2/trunk/fpga/top/u2plus
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From: |
matt |
|
Subject: |
[Commit-gnuradio] r8234 - usrp2/trunk/fpga/top/u2plus |
|
Date: |
Mon, 21 Apr 2008 12:07:46 -0600 (MDT) |
Author: matt
Date: 2008-04-21 12:07:46 -0600 (Mon, 21 Apr 2008)
New Revision: 8234
Added:
usrp2/trunk/fpga/top/u2plus/u2plus.ucf
usrp2/trunk/fpga/top/u2plus/u2plus.v
Log:
copied over from u2_rev2
Added: usrp2/trunk/fpga/top/u2plus/u2plus.ucf
===================================================================
--- usrp2/trunk/fpga/top/u2plus/u2plus.ucf (rev 0)
+++ usrp2/trunk/fpga/top/u2plus/u2plus.ucf 2008-04-21 18:07:46 UTC (rev
8234)
@@ -0,0 +1,327 @@
+NET "leds[0]" LOC = "F7" ;
+NET "leds[1]" LOC = "E5" ;
+NET "leds[2]" LOC = "B7" ;
+NET "leds[3]" LOC = "C11" ;
+NET "leds[4]" LOC = "AB19" ;
+NET "debug[0]" LOC = "N5" ;
+NET "debug[1]" LOC = "N6" ;
+NET "debug[2]" LOC = "P1" ;
+NET "debug[3]" LOC = "P2" ;
+NET "debug[4]" LOC = "P4" ;
+NET "debug[5]" LOC = "P5" ;
+NET "debug[6]" LOC = "R1" ;
+NET "debug[7]" LOC = "R2" ;
+NET "debug[8]" LOC = "P6" ;
+NET "debug[9]" LOC = "R5" ;
+NET "debug[10]" LOC = "R4" ;
+NET "debug[11]" LOC = "T3" ;
+NET "debug[12]" LOC = "U3" ;
+NET "debug[13]" LOC = "M2" ;
+NET "debug[14]" LOC = "M3" ;
+NET "debug[15]" LOC = "M4" ;
+NET "debug[16]" LOC = "M5" ;
+NET "debug[17]" LOC = "M6" ;
+NET "debug[18]" LOC = "N1" ;
+NET "debug[19]" LOC = "N2" ;
+NET "debug[20]" LOC = "N3" ;
+NET "debug[21]" LOC = "T1" ;
+NET "debug[22]" LOC = "T2" ;
+NET "debug[23]" LOC = "U2" ;
+NET "debug[24]" LOC = "T4" ;
+NET "debug[25]" LOC = "U4" ;
+NET "debug[26]" LOC = "T5" ;
+NET "debug[27]" LOC = "T6" ;
+NET "debug[28]" LOC = "U5" ;
+NET "debug[29]" LOC = "V5" ;
+NET "debug[30]" LOC = "W2" ;
+NET "debug[31]" LOC = "W3" ;
+NET "debug_clk[0]" LOC = "N4" ;
+NET "debug_clk[1]" LOC = "M1" ;
+NET "uart_tx_o" LOC = "C7" ;
+NET "uart_rx_i" LOC = "A3" ;
+NET "exp_pps_in_p" LOC = "V3" ;
+NET "exp_pps_in_n" LOC = "V4" ;
+NET "exp_pps_out_p" LOC = "V1" ;
+NET "exp_pps_out_n" LOC = "V2" ;
+NET "GMII_COL" LOC = "U16" ;
+NET "GMII_CRS" LOC = "U17" ;
+NET "GMII_TXD[0]" LOC = "W14" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW
= FAST ;
+NET "GMII_TXD[1]" LOC = "AA20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW
= FAST ;
+NET "GMII_TXD[2]" LOC = "AB20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW
= FAST ;
+NET "GMII_TXD[3]" LOC = "Y18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW
= FAST ;
+NET "GMII_TXD[4]" LOC = "AA18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW
= FAST ;
+NET "GMII_TXD[5]" LOC = "AB18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW
= FAST ;
+NET "GMII_TXD[6]" LOC = "V17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW
= FAST ;
+NET "GMII_TXD[7]" LOC = "W17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW
= FAST ;
+NET "GMII_TX_EN" LOC = "Y17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "GMII_TX_ER" LOC = "V16" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "GMII_GTX_CLK" LOC = "AA17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW
= FAST ;
+NET "GMII_TX_CLK" LOC = "W13" ;
+NET "GMII_RXD[0]" LOC = "AA15" ;
+NET "GMII_RXD[1]" LOC = "AB15" ;
+NET "GMII_RXD[2]" LOC = "U14" ;
+NET "GMII_RXD[3]" LOC = "V14" ;
+NET "GMII_RXD[4]" LOC = "U13" ;
+NET "GMII_RXD[5]" LOC = "V13" ;
+NET "GMII_RXD[6]" LOC = "Y13" ;
+NET "GMII_RXD[7]" LOC = "AA13" ;
+NET "GMII_RX_CLK" LOC = "W16" ;
+NET "GMII_RX_DV" LOC = "AB16" ;
+NET "GMII_RX_ER" LOC = "AA16" ;
+NET "MDIO" LOC = "Y16" | PULLUP ;
+NET "MDC" LOC = "V18" ;
+NET "PHY_INTn" LOC = "AB13" ;
+NET "PHY_RESETn" LOC = "AA19" ;
+NET "PHY_CLK" LOC = "V15" ;
+NET "RAM_D[0]" LOC = "N20" ;
+NET "RAM_D[1]" LOC = "N21" ;
+NET "RAM_D[2]" LOC = "N22" ;
+NET "RAM_D[3]" LOC = "M17" ;
+NET "RAM_D[4]" LOC = "M18" ;
+NET "RAM_D[5]" LOC = "M19" ;
+NET "RAM_D[6]" LOC = "M20" ;
+NET "RAM_D[7]" LOC = "M21" ;
+NET "RAM_D[8]" LOC = "M22" ;
+NET "RAM_D[9]" LOC = "Y22" ;
+NET "RAM_D[10]" LOC = "Y21" ;
+NET "RAM_D[11]" LOC = "Y20" ;
+NET "RAM_D[12]" LOC = "Y19" ;
+NET "RAM_D[13]" LOC = "W22" ;
+NET "RAM_D[14]" LOC = "W21" ;
+NET "RAM_D[15]" LOC = "W20" ;
+NET "RAM_D[16]" LOC = "W19" ;
+NET "RAM_D[17]" LOC = "V22" ;
+NET "RAM_A[0]" LOC = "U21" ;
+NET "RAM_A[1]" LOC = "T19" ;
+NET "RAM_A[2]" LOC = "V21" ;
+NET "RAM_A[3]" LOC = "V20" ;
+NET "RAM_A[4]" LOC = "T20" ;
+NET "RAM_A[5]" LOC = "T21" ;
+NET "RAM_A[6]" LOC = "T22" ;
+NET "RAM_A[7]" LOC = "T18" ;
+NET "RAM_A[8]" LOC = "R18" ;
+NET "RAM_A[9]" LOC = "P19" ;
+NET "RAM_A[10]" LOC = "P21" ;
+NET "RAM_A[11]" LOC = "P22" ;
+NET "RAM_A[12]" LOC = "N19" ;
+NET "RAM_A[13]" LOC = "N17" ;
+NET "RAM_A[14]" LOC = "N18" ;
+NET "RAM_A[15]" LOC = "T17" ;
+NET "RAM_A[16]" LOC = "U19" ;
+NET "RAM_A[17]" LOC = "U18" ;
+NET "RAM_A[18]" LOC = "V19" ;
+NET "RAM_CE1n" LOC = "U20" ;
+NET "RAM_CENn" LOC = "P18" ;
+NET "RAM_CLK" LOC = "P17" ;
+NET "RAM_WEn" LOC = "R22" ;
+NET "RAM_OEn" LOC = "R21" ;
+NET "RAM_LDn" LOC = "R19" ;
+NET "ser_enable" LOC = "W11" ;
+NET "ser_prbsen" LOC = "AA3" ;
+NET "ser_loopen" LOC = "Y4" ;
+NET "ser_rx_en" LOC = "AB9" ;
+NET "ser_tx_clk" LOC = "U7" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_t[0]" LOC = "V7" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_t[1]" LOC = "V10" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_t[2]" LOC = "AB4" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_t[3]" LOC = "AA4" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_t[4]" LOC = "Y5" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_t[5]" LOC = "W5" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_t[6]" LOC = "AB5" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_t[7]" LOC = "AA5" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_t[8]" LOC = "W6" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_t[9]" LOC = "V6" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_t[10]" LOC = "AA6" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_t[11]" LOC = "Y6" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_t[12]" LOC = "W8" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_t[13]" LOC = "V8" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_t[14]" LOC = "AB8" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_t[15]" LOC = "AA8" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_tklsb" LOC = "U10" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_tkmsb" LOC = "U11" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW =
FAST ;
+NET "ser_rx_clk" LOC = "AA11" ;
+NET "ser_r[0]" LOC = "AB10" ;
+NET "ser_r[1]" LOC = "AA10" ;
+NET "ser_r[2]" LOC = "U9" ;
+NET "ser_r[3]" LOC = "U6" ;
+NET "ser_r[4]" LOC = "AB11" ;
+NET "ser_r[5]" LOC = "Y7" ;
+NET "ser_r[6]" LOC = "W7" ;
+NET "ser_r[7]" LOC = "AB7" ;
+NET "ser_r[8]" LOC = "AA7" ;
+NET "ser_r[9]" LOC = "W9" ;
+NET "ser_r[10]" LOC = "W10" ;
+NET "ser_r[11]" LOC = "Y1" ;
+NET "ser_r[12]" LOC = "Y3" ;
+NET "ser_r[13]" LOC = "Y2" ;
+NET "ser_r[14]" LOC = "W4" ;
+NET "ser_r[15]" LOC = "W1" ;
+NET "ser_rklsb" LOC = "V9" ;
+NET "ser_rkmsb" LOC = "Y10" ;
+NET "cpld_start" LOC = "AA9" ;
+NET "cpld_mode" LOC = "U12" ;
+NET "cpld_done" LOC = "V12" ;
+NET "cpld_din" LOC = "AA14" ;
+NET "cpld_clk" LOC = "AB14" ;
+NET "cpld_detached" LOC = "V11" ;
+NET "cpld_init_b" LOC = "W12" ;
+NET "cpld_misc" LOC = "Y12" ;
+NET "adc_a[0]" LOC = "A14" ;
+NET "adc_a[1]" LOC = "B14" ;
+NET "adc_a[2]" LOC = "C13" ;
+NET "adc_a[3]" LOC = "D13" ;
+NET "adc_a[4]" LOC = "A13" ;
+NET "adc_a[5]" LOC = "B13" ;
+NET "adc_a[6]" LOC = "E12" ;
+NET "adc_a[7]" LOC = "C22" ;
+NET "adc_a[8]" LOC = "C20" ;
+NET "adc_a[9]" LOC = "C21" ;
+NET "adc_a[10]" LOC = "D20" ;
+NET "adc_a[11]" LOC = "D19" ;
+NET "adc_a[12]" LOC = "D21" ;
+NET "adc_a[13]" LOC = "E18" ;
+NET "adc_ovf_a" LOC = "F18" ;
+NET "adc_oen_a" LOC = "E19" ;
+NET "adc_pdn_a" LOC = "E20" ;
+NET "adc_b[0]" LOC = "A12" ;
+NET "adc_b[1]" LOC = "E16" ;
+NET "adc_b[2]" LOC = "F12" ;
+NET "adc_b[3]" LOC = "F13" ;
+NET "adc_b[4]" LOC = "F16" ;
+NET "adc_b[5]" LOC = "F17" ;
+NET "adc_b[6]" LOC = "C19" ;
+NET "adc_b[7]" LOC = "B20" ;
+NET "adc_b[8]" LOC = "B19" ;
+NET "adc_b[9]" LOC = "C18" ;
+NET "adc_b[10]" LOC = "D18" ;
+NET "adc_b[11]" LOC = "B18" ;
+NET "adc_b[12]" LOC = "D17" ;
+NET "adc_b[13]" LOC = "E17" ;
+NET "adc_ovf_b" LOC = "B17" ;
+NET "adc_oen_b" LOC = "C17" ;
+NET "adc_pdn_b" LOC = "D15" ;
+NET "dac_a[0]" LOC = "A5" ;
+NET "dac_a[1]" LOC = "B5" ;
+NET "dac_a[2]" LOC = "C5" ;
+NET "dac_a[3]" LOC = "D5" ;
+NET "dac_a[4]" LOC = "A4" ;
+NET "dac_a[5]" LOC = "B4" ;
+NET "dac_a[6]" LOC = "F6" ;
+NET "dac_a[7]" LOC = "D10" ;
+NET "dac_a[8]" LOC = "D9" ;
+NET "dac_a[9]" LOC = "A10" ;
+NET "dac_a[10]" LOC = "L2" ;
+NET "dac_a[11]" LOC = "L4" ;
+NET "dac_a[12]" LOC = "L3" ;
+NET "dac_a[13]" LOC = "L6" ;
+NET "dac_a[14]" LOC = "L5" ;
+NET "dac_a[15]" LOC = "K2" ;
+NET "dac_b[0]" LOC = "D11" ;
+NET "dac_b[1]" LOC = "E11" ;
+NET "dac_b[2]" LOC = "F11" ;
+NET "dac_b[3]" LOC = "B10" ;
+NET "dac_b[4]" LOC = "C10" ;
+NET "dac_b[5]" LOC = "E10" ;
+NET "dac_b[6]" LOC = "F10" ;
+NET "dac_b[7]" LOC = "A9" ;
+NET "dac_b[8]" LOC = "B9" ;
+NET "dac_b[9]" LOC = "E9" ;
+NET "dac_b[10]" LOC = "F9" ;
+NET "dac_b[11]" LOC = "A8" ;
+NET "dac_b[12]" LOC = "B8" ;
+NET "dac_b[13]" LOC = "D7" ;
+NET "dac_b[14]" LOC = "E7" ;
+NET "dac_b[15]" LOC = "B6" ;
+NET "dac_lock" LOC = "D6" ;
+NET "SCL" LOC = "A7" ;
+NET "SDA" LOC = "D8" ;
+NET "clk_en[0]" LOC = "C4" ;
+NET "clk_en[1]" LOC = "D1" ;
+NET "clk_sel[0]" LOC = "C3" ;
+NET "clk_sel[1]" LOC = "C2" ;
+NET "clk_func" LOC = "C12" ;
+NET "clk_status" LOC = "B12" ;
+NET "clk_fpga_p" LOC = "A11" ;
+NET "clk_fpga_n" LOC = "B11" ;
+NET "clk_to_mac" LOC = "AB12" ;
+NET "pps_in" LOC = "Y11" ;
+NET "sclk" LOC = "K5" ;
+NET "sen_clk" LOC = "K6" ;
+NET "sen_dac" LOC = "L1" ;
+NET "sdi" LOC = "J1" ;
+NET "sdo" LOC = "J2" ;
+NET "sen_tx_db" LOC = "C1" ;
+NET "sclk_tx_db" LOC = "D3" ;
+NET "sdo_tx_db" LOC = "G3" ;
+NET "sdi_tx_db" LOC = "G4" ;
+NET "sen_tx_adc" LOC = "G2" ;
+NET "sclk_tx_adc" LOC = "H1" ;
+NET "sdo_tx_adc" LOC = "H2" ;
+NET "sdi_tx_adc" LOC = "J4" ;
+NET "sen_tx_dac" LOC = "H4" ;
+NET "sclk_tx_dac" LOC = "J5" ;
+NET "sdi_tx_dac" LOC = "J6" ;
+NET "io_tx[0]" LOC = "K4" ;
+NET "io_tx[1]" LOC = "K3" ;
+NET "io_tx[2]" LOC = "G1" ;
+NET "io_tx[3]" LOC = "G5" ;
+NET "io_tx[4]" LOC = "H5" ;
+NET "io_tx[5]" LOC = "F3" ;
+NET "io_tx[6]" LOC = "F2" ;
+NET "io_tx[7]" LOC = "F5" ;
+NET "io_tx[8]" LOC = "G6" ;
+NET "io_tx[9]" LOC = "E2" ;
+NET "io_tx[10]" LOC = "E1" ;
+NET "io_tx[11]" LOC = "E3" ;
+NET "io_tx[12]" LOC = "F4" ;
+NET "io_tx[13]" LOC = "D2" ;
+NET "io_tx[14]" LOC = "D4" ;
+NET "io_tx[15]" LOC = "E4" ;
+NET "sen_rx_db" LOC = "D22" ;
+NET "sclk_rx_db" LOC = "F19" ;
+NET "sdo_rx_db" LOC = "G20" ;
+NET "sdi_rx_db" LOC = "H19" ;
+NET "sen_rx_adc" LOC = "H18" ;
+NET "sclk_rx_adc" LOC = "J17" ;
+NET "sdo_rx_adc" LOC = "H21" ;
+NET "sdi_rx_adc" LOC = "H22" ;
+NET "sen_rx_dac" LOC = "J18" ;
+NET "sclk_rx_dac" LOC = "J19" ;
+NET "sdi_rx_dac" LOC = "J21" ;
+NET "io_rx[0]" LOC = "L21" ;
+NET "io_rx[1]" LOC = "L20" ;
+NET "io_rx[2]" LOC = "L19" ;
+NET "io_rx[3]" LOC = "L18" ;
+NET "io_rx[4]" LOC = "L17" ;
+NET "io_rx[5]" LOC = "K22" ;
+NET "io_rx[6]" LOC = "K21" ;
+NET "io_rx[7]" LOC = "K20" ;
+NET "io_rx[8]" LOC = "G22" ;
+NET "io_rx[9]" LOC = "G21" ;
+NET "io_rx[10]" LOC = "F21" ;
+NET "io_rx[11]" LOC = "F20" ;
+NET "io_rx[12]" LOC = "G19" ;
+NET "io_rx[13]" LOC = "G18" ;
+NET "io_rx[14]" LOC = "G17" ;
+NET "io_rx[15]" LOC = "E22" ;
+
+
+NET "clk_muxed" TNM_NET = "clk_muxed";
+TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %;
+
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+
+
+NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
+NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE;
+NET "PHY_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
Property changes on: usrp2/trunk/fpga/top/u2plus/u2plus.ucf
___________________________________________________________________
Name: svn:executable
+ *
Added: usrp2/trunk/fpga/top/u2plus/u2plus.v
===================================================================
--- usrp2/trunk/fpga/top/u2plus/u2plus.v (rev 0)
+++ usrp2/trunk/fpga/top/u2plus/u2plus.v 2008-04-21 18:07:46 UTC (rev
8234)
@@ -0,0 +1,393 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u2plus
+ (
+ // Misc, debug
+ output [4:0] leds,
+ output [31:0] debug,
+ output [1:0] debug_clk,
+ output uart_tx_o,
+ input uart_rx_i,
+
+ // Expansion
+ input exp_pps_in_p, // Diff
+ input exp_pps_in_n, // Diff
+ output exp_pps_out_p, // Diff
+ output exp_pps_out_n, // Diff
+
+ // GMII
+ // GMII-CTRL
+ input GMII_COL,
+ input GMII_CRS,
+
+ // GMII-TX
+ output reg [7:0] GMII_TXD,
+ output reg GMII_TX_EN,
+ output reg GMII_TX_ER,
+ output GMII_GTX_CLK,
+ input GMII_TX_CLK, // 100mbps clk
+
+ // GMII-RX
+ input [7:0] GMII_RXD,
+ input GMII_RX_CLK,
+ input GMII_RX_DV,
+ input GMII_RX_ER,
+
+ // GMII-Management
+ inout MDIO,
+ output MDC,
+ input PHY_INTn, // open drain
+ output PHY_RESETn,
+ input PHY_CLK, // possibly use on-board osc
+
+ // RAM
+ inout [17:0] RAM_D,
+ output [18:0] RAM_A,
+ output RAM_CE1n,
+ output RAM_CENn,
+ output RAM_CLK,
+ output RAM_WEn,
+ output RAM_OEn,
+ output RAM_LDn,
+
+ // SERDES
+ output ser_enable,
+ output ser_prbsen,
+ output ser_loopen,
+ output ser_rx_en,
+
+ output ser_tx_clk,
+ output reg [15:0] ser_t,
+ output reg ser_tklsb,
+ output reg ser_tkmsb,
+
+ input ser_rx_clk,
+ input [15:0] ser_r,
+ input ser_rklsb,
+ input ser_rkmsb,
+
+ // CPLD interface
+ output cpld_start, // AA9
+ output cpld_mode, // U12
+ output cpld_done, // V12
+ input cpld_din, // AA14 Now shared with CFG_Din
+ input cpld_clk, // AB14 serial clock
+ input cpld_detached,// V11 unused
+ input cpld_init_b, // W12 unused dual purpose
+ input cpld_misc, // Y12 unused
+
+ // ADC
+ input [13:0] adc_a,
+ input adc_ovf_a,
+ output adc_oen_a,
+ output adc_pdn_a,
+
+ input [13:0] adc_b,
+ input adc_ovf_b,
+ output adc_oen_b,
+ output adc_pdn_b,
+
+ // DAC
+ output [15:0] dac_a,
+ output [15:0] dac_b,
+ input dac_lock, // unused for now
+
+ // I2C
+ inout SCL,
+ inout SDA,
+
+ // Clock Gen Control
+ output [1:0] clk_en,
+ output [1:0] clk_sel,
+ input clk_func, // FIXME is an input to control the 9510
+ input clk_status,
+
+ // Clocks
+ input clk_fpga_p, // Diff
+ input clk_fpga_n, // Diff
+ input clk_to_mac,
+ input pps_in,
+
+ // Generic SPI
+ output sclk,
+ output sen_clk,
+ output sen_dac,
+ output sdi,
+ input sdo,
+
+ // TX DBoard
+ output sen_tx_db,
+ output sclk_tx_db,
+ input sdo_tx_db,
+ output sdi_tx_db,
+
+ output sen_tx_adc,
+ output sclk_tx_adc,
+ input sdo_tx_adc,
+ output sdi_tx_adc,
+
+ output sen_tx_dac,
+ output sclk_tx_dac,
+ output sdi_tx_dac,
+
+ inout [15:0] io_tx,
+
+ // RX DBoard
+ output sen_rx_db,
+ output sclk_rx_db,
+ input sdo_rx_db,
+ output sdi_rx_db,
+
+ output sen_rx_adc,
+ output sclk_rx_adc,
+ input sdo_rx_adc,
+ output sdi_rx_adc,
+
+ output sen_rx_dac,
+ output sclk_rx_dac,
+ output sdi_rx_dac,
+
+ inout [15:0] io_rx
+ );
+
+ // FPGA-specific pins connections
+ wire aux_clk = PHY_CLK;
+
+ wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+
+ IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+ defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+
+ wire exp_pps_in;
+ IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
+ defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+
+ wire exp_pps_out;
+ OBUFDS exp_pps_out_pin
(.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
+ defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+
+ reg [5:0] clock_ready_d;
+ always @(posedge aux_clk)
+ clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
+
+ wire dcm_rst = ~&clock_ready_d & |clock_ready_d;
+ wire clk_muxed = clock_ready ? clk_fpga : aux_clk;
+
+ wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
+ assign adc_oen_a = ~adc_oe_a;
+ assign adc_oen_b = ~adc_oe_b;
+ assign adc_pdn_a = ~adc_on_a;
+ assign adc_pdn_b = ~adc_on_b;
+
+ // Handle Clocks
+ DCM DCM_INST (.CLKFB(dsp_clk),
+ .CLKIN(clk_muxed),
+ .DSSEN(0),
+ .PSCLK(0),
+ .PSEN(0),
+ .PSINCDEC(0),
+ .RST(dcm_rst),
+ .CLKDV(clk_div),
+ .CLKFX(),
+ .CLKFX180(),
+ .CLK0(dcm_out),
+ .CLK2X(),
+ .CLK2X180(),
+ .CLK90(),
+ .CLK180(),
+ .CLK270(),
+ .LOCKED(LOCKED_OUT),
+ .PSDONE(),
+ .STATUS());
+ defparam DCM_INST.CLK_FEEDBACK = "1X";
+ defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+ defparam DCM_INST.CLKFX_DIVIDE = 1;
+ defparam DCM_INST.CLKFX_MULTIPLY = 4;
+ defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+ defparam DCM_INST.CLKIN_PERIOD = 10.000;
+ defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+ defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+ defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+ defparam DCM_INST.FACTORY_JF = 16'h8080;
+ defparam DCM_INST.PHASE_SHIFT = 0;
+ defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+ BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+ BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+ // I2C -- Don't use external transistors for open drain, the FPGA
implements this
+ IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+ IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+ // LEDs are active low outputs
+ wire [4:0] leds_int;
+ assign leds = ~leds_int; // drive low to turn on leds
+
+ // SPI
+ wire miso, mosi, sclk_int;
+ assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
+
+ assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) |
+ (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
+ (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+
+ wire GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+ wire [7:0] GMII_TXD_unreg;
+ wire GMII_GTX_CLK_int;
+
+ always @(posedge GMII_GTX_CLK_int)
+ begin
+ GMII_TX_EN <= GMII_TX_EN_unreg;
+ GMII_TX_ER <= GMII_TX_ER_unreg;
+ GMII_TXD <= GMII_TXD_unreg;
+ end
+
+ OFDDRRSE OFDDRRSE_gmii_inst
+ (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level
port)
+ .C0(GMII_GTX_CLK_int), // 0 degree clock input
+ .C1(~GMII_GTX_CLK_int), // 180 degree clock input
+ .CE(1), // Clock enable input
+ .D0(0), // Posedge data input
+ .D1(1), // Negedge data input
+ .R(0), // Synchronous reset input
+ .S(0) // Synchronous preset input
+ );
+
+ wire ser_tklsb_unreg, ser_tkmsb_unreg;
+ wire [15:0] ser_t_unreg;
+ wire ser_tx_clk_int;
+
+ always @(posedge ser_tx_clk_int)
+ begin
+ ser_tklsb <= ser_tklsb_unreg;
+ ser_tkmsb <= ser_tkmsb_unreg;
+ ser_t <= ser_t_unreg;
+ end
+
+ assign ser_tx_clk = clk_fpga;
+
+ reg [15:0] ser_r_int;
+ reg ser_rklsb_int, ser_rkmsb_int;
+
+ always @(posedge ser_rx_clk)
+ begin
+ ser_r_int <= ser_r;
+ ser_rklsb_int <= ser_rklsb;
+ ser_rkmsb_int <= ser_rkmsb;
+ end
+
+ /*
+ OFDDRRSE OFDDRRSE_serdes_inst
+ (.Q(ser_tx_clk), // Data output (connect directly to top-level port)
+ .C0(ser_tx_clk_int), // 0 degree clock input
+ .C1(~ser_tx_clk_int), // 180 degree clock input
+ .CE(1), // Clock enable input
+ .D0(0), // Posedge data input
+ .D1(1), // Negedge data input
+ .R(0), // Synchronous reset input
+ .S(0) // Synchronous preset input
+ );
+ */
+ u2_core u2_core(.dsp_clk (dsp_clk),
+ .wb_clk (wb_clk),
+ .clock_ready (clock_ready),
+ .clk_to_mac (clk_to_mac),
+ .pps_in (pps_in),
+ .leds (leds_int),
+ .debug (debug[31:0]),
+ .debug_clk (debug_clk[1:0]),
+ .exp_pps_in (exp_pps_in),
+ .exp_pps_out (exp_pps_out),
+ .GMII_COL (GMII_COL),
+ .GMII_CRS (GMII_CRS),
+ .GMII_TXD (GMII_TXD_unreg[7:0]),
+ .GMII_TX_EN (GMII_TX_EN_unreg),
+ .GMII_TX_ER (GMII_TX_ER_unreg),
+ .GMII_GTX_CLK (GMII_GTX_CLK_int),
+ .GMII_TX_CLK (GMII_TX_CLK),
+ .GMII_RXD (GMII_RXD[7:0]),
+ .GMII_RX_CLK (GMII_RX_CLK),
+ .GMII_RX_DV (GMII_RX_DV),
+ .GMII_RX_ER (GMII_RX_ER),
+ .MDIO (MDIO),
+ .MDC (MDC),
+ .PHY_INTn (PHY_INTn),
+ .PHY_RESETn (PHY_RESETn),
+ .PHY_CLK (PHY_CLK),
+ .ser_enable (ser_enable),
+ .ser_prbsen (ser_prbsen),
+ .ser_loopen (ser_loopen),
+ .ser_rx_en (ser_rx_en),
+ .ser_tx_clk (ser_tx_clk_int),
+ .ser_t (ser_t_unreg[15:0]),
+ .ser_tklsb (ser_tklsb_unreg),
+ .ser_tkmsb (ser_tkmsb_unreg),
+ .ser_rx_clk (ser_rx_clk),
+ .ser_r (ser_r_int[15:0]),
+ .ser_rklsb (ser_rklsb_int),
+ .ser_rkmsb (ser_rkmsb_int),
+ .cpld_start (cpld_start),
+ .cpld_mode (cpld_mode),
+ .cpld_done (cpld_done),
+ .cpld_din (cpld_din),
+ .cpld_clk (cpld_clk),
+ .cpld_detached (cpld_detached),
+ .adc_a (adc_a[13:0]),
+ .adc_ovf_a (adc_ovf_a),
+ .adc_on_a (adc_on_a),
+ .adc_oe_a (adc_oe_a),
+ .adc_b (adc_b[13:0]),
+ .adc_ovf_b (adc_ovf_b),
+ .adc_on_b (adc_on_b),
+ .adc_oe_b (adc_oe_b),
+ .dac_a (dac_a[15:0]),
+ .dac_b (dac_b[15:0]),
+ .scl_pad_i (scl_pad_i),
+ .scl_pad_o (scl_pad_o),
+ .scl_pad_oen_o (scl_pad_oen_o),
+ .sda_pad_i (sda_pad_i),
+ .sda_pad_o (sda_pad_o),
+ .sda_pad_oen_o (sda_pad_oen_o),
+ .clk_en (clk_en[1:0]),
+ .clk_sel (clk_sel[1:0]),
+ .clk_func (clk_func),
+ .clk_status (clk_status),
+ .sclk (sclk_int),
+ .mosi (mosi),
+ .miso (miso),
+ .sen_clk (sen_clk),
+ .sen_dac (sen_dac),
+ .sen_tx_db (sen_tx_db),
+ .sen_tx_adc (sen_tx_adc),
+ .sen_tx_dac (sen_tx_dac),
+ .sen_rx_db (sen_rx_db),
+ .sen_rx_adc (sen_rx_adc),
+ .sen_rx_dac (sen_rx_dac),
+ .io_tx (io_tx[15:0]),
+ .io_rx (io_rx[15:0]),
+ .RAM_D (RAM_D),
+ .RAM_A (RAM_A),
+ .RAM_CE1n (RAM_CE1n),
+ .RAM_CENn (RAM_CENn),
+ .RAM_CLK (RAM_CLK),
+ .RAM_WEn (RAM_WEn),
+ .RAM_OEn (RAM_OEn),
+ .RAM_LDn (RAM_LDn),
+ .uart_tx_o (uart_tx_o),
+ //.uart_rx_i (uart_rx_i),
+ .uart_rx_i (),
+ .uart_baud_o (),
+ .sim_mode (1'b0),
+ .clock_divider (2)
+ );
+
+endmodule // u2plus
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