[Commit-gnuradio] r8248 - usrp2/trunk/fpga/control_lib

[matt]

Author: matt
Date: 2008-04-23 13:54:16 -0600 (Wed, 23 Apr 2008)
New Revision: 8248

Modified:
   usrp2/trunk/fpga/control_lib/dpram32.v
   usrp2/trunk/fpga/control_lib/ram_harv_cache.v
Log:
RAM size is now parameterizable separately from address width.  This allows, 
e.g. 24K of RAM.


Modified: usrp2/trunk/fpga/control_lib/dpram32.v
===================================================================
--- usrp2/trunk/fpga/control_lib/dpram32.v      2008-04-23 19:52:38 UTC (rev 
8247)
+++ usrp2/trunk/fpga/control_lib/dpram32.v      2008-04-23 19:54:16 UTC (rev 
8248)
@@ -1,10 +1,12 @@
 
 // Dual ported RAM
 //    Addresses are byte-oriented, so botton 2 address bits are ignored.
-//    AWIDTH of 13 gives 8K bytes.  For Spartan 3, if the total RAM size is 
not a
-//    multiple of 8K then BRAM space is wasted
+//    AWIDTH of 13 allows you to address 8K bytes.  
+//    For Spartan 3, if the total RAM size is not a multiple of 8K then BRAM 
space is wasted
+// RAM_SIZE parameter allows odd-sized RAMs, like 24K
 
-module dpram32 #(parameter AWIDTH=13)
+module dpram32 #(parameter AWIDTH=15, 
+                parameter RAM_SIZE=16384)
   (input clk,
    
    input [AWIDTH-1:0] adr1_i,
@@ -21,10 +23,13 @@
    input en2_i,
    input [3:0] sel2_i );
    
-   reg [7:0]   ram0 [0:(1<<(AWIDTH-2))-1];
-   reg [7:0]   ram1 [0:(1<<(AWIDTH-2))-1];
-   reg [7:0]   ram2 [0:(1<<(AWIDTH-2))-1];
-   reg [7:0]   ram3 [0:(1<<(AWIDTH-2))-1];
+   reg [7:0]   ram0 [0:(RAM_SIZE/4)-1];
+   reg [7:0]   ram1 [0:(RAM_SIZE/4)-1];
+   reg [7:0]   ram2 [0:(RAM_SIZE/4)-1];
+   reg [7:0]   ram3 [0:(RAM_SIZE/4)-1];
+
+   //  This is how we used to size the RAM -->  
+   //      reg [7:0]   ram3 [0:(1<<(AWIDTH-2))-1];
    
    // Port 1
    always @(posedge clk)

Modified: usrp2/trunk/fpga/control_lib/ram_harv_cache.v
===================================================================
--- usrp2/trunk/fpga/control_lib/ram_harv_cache.v       2008-04-23 19:52:38 UTC 
(rev 8247)
+++ usrp2/trunk/fpga/control_lib/ram_harv_cache.v       2008-04-23 19:54:16 UTC 
(rev 8248)
@@ -3,7 +3,7 @@
 // Dual ported, Harvard architecture, cached ram
 
 module ram_harv_cache
-  #(parameter AWIDTH=14,parameter ICWIDTH=6,parameter DCWIDTH=6)
+  #(parameter AWIDTH=15,parameter RAM_SIZE=16384,parameter ICWIDTH=6,parameter 
DCWIDTH=6)
     (input wb_clk_i, input wb_rst_i,
      
      input [AWIDTH-1:0] ram_loader_adr_i,