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[Commit-gnuradio] r8383 - usrp2/trunk/firmware/lib
From: |
matt |
Subject: |
[Commit-gnuradio] r8383 - usrp2/trunk/firmware/lib |
Date: |
Sun, 11 May 2008 11:13:56 -0600 (MDT) |
Author: matt
Date: 2008-05-11 11:13:56 -0600 (Sun, 11 May 2008)
New Revision: 8383
Modified:
usrp2/trunk/firmware/lib/u2_init.c
Log:
changes for rev2 which were never checked in before. Turns on the ADC clock
Modified: usrp2/trunk/firmware/lib/u2_init.c
===================================================================
--- usrp2/trunk/firmware/lib/u2_init.c 2008-05-11 06:39:11 UTC (rev 8382)
+++ usrp2/trunk/firmware/lib/u2_init.c 2008-05-11 17:13:56 UTC (rev 8383)
@@ -79,13 +79,14 @@
ad9510_write_reg(0x08, 0x47);
}
else {
- // Reg 8, Charge pump off, dig lock det, positive PFD, 47
+ // Reg 8, Charge pump off, dig lock det, positive PFD
ad9510_write_reg(0x08, 0x00);
}
// Reg 9, Charge pump current, 3mA, 40
- ad9510_write_reg(0x09, 0x40);
- // Reg A, Prescalar of 2, everything normal 04
+ //ad9510_write_reg(0x09, 0x40);
+ ad9510_write_reg(0x09, 0x0);
+ // Reg A, Prescaler of 2, everything normal 04
ad9510_write_reg(0x0A, 0x04);
// Reg B, R Div MSBs, 0
ad9510_write_reg(0x0B, 0x00);
@@ -104,16 +105,23 @@
}
else if (LOCK_TO_EXT_REF) {
// turn on ref output and choose the SMA
- output_regs->clk_ctrl = 0x14;
+ output_regs->clk_ctrl = 0x1C;
}
else if (LOCK_TO_MIMO_REF) {
// Turn on ref output and choose the MIMO connector
output_regs->clk_ctrl = 0x15;
}
+#define TEST_CLK 1
+
// Set up other clocks
- ad9510_write_reg(0x3C, 0x02); // Turn off output 0 (unused)
-
+ if(TEST_CLK) {
+ ad9510_write_reg(0x3C, 0x08); // Turn on output 0 -- Test output
+ ad9510_write_reg(0x49, 0x80); // Bypass divider 0
+ } else {
+ ad9510_write_reg(0x3C, 0x02); // Turn off output 0
+ }
+
if (THEY_LOCK_TO_ME) {
ad9510_write_reg(0x3E, 0x00); // Turn on output 2 (clk_exp_out), normal
levels
ad9510_write_reg(0x4D, 0x00); // Turn on Div2
@@ -123,7 +131,13 @@
ad9510_write_reg(0x3E, 0x02); // Turn off output 2 (clk_exp_out)
ad9510_write_reg(0x4D, 0x80); // Bypass divider 2
}
- ad9510_write_reg(0x40, 0x01); // Turn off output 4 (phy_clk)
+
+#define REV2 1
+ if (REV2)
+ ad9510_write_reg(0x41, 0x01); // Turn off output 5 (phy_clk)
+ else
+ ad9510_write_reg(0x40, 0x01); // Turn off output 4 (phy_clk)
+
ad9510_write_reg(0x42, 0x01); // Turn off output 6 (db_tx_clk)
ad9510_write_reg(0x43, 0x01); // Turn off output 7 (db_rx_clk)
ad9510_write_reg(0x5A, 0x01); // Update Regs
@@ -133,9 +147,17 @@
// Enable clock to ADCs and DACs
ad9510_write_reg(0x3F, 0x00); // Turn on output 3 (DAC CLK), normal levels
- ad9510_write_reg(0x41, 0x08); // Turn on out 5 (ADC clk), CMOS
ad9510_write_reg(0x4F, 0x80); // Bypass Div #3
- ad9510_write_reg(0x53, 0x80); // Bypass Div #5
+ if (REV2) {
+ ad9510_write_reg(0x40, 0x08); // Turn on out 4 (ADC clk), CMOS
+ ad9510_write_reg(0x52, 0x80); // Bypass Div #4
+ } else {
+ ad9510_write_reg(0x41, 0x08); // Turn on out 5 (ADC clk), CMOS
+ ad9510_write_reg(0x53, 0x80); // Bypass Div #5
+ }
+
+ ad9510_write_reg(0x52, 0x11);
+ ad9510_write_reg(0x53, 0x0);
ad9510_write_reg(0x5A, 0x01); // Update Regs
// FIXME clean this up.
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