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[Commit-gnuradio] r8430 - in gnuradio/branches/developers/gnychis/fpga/u
From: |
gnychis |
Subject: |
[Commit-gnuradio] r8430 - in gnuradio/branches/developers/gnychis/fpga/usrp/fpga: inband_lib toplevel/usrp_inband_usb |
Date: |
Thu, 15 May 2008 11:43:57 -0600 (MDT) |
Author: gnychis
Date: 2008-05-15 11:43:55 -0600 (Thu, 15 May 2008)
New Revision: 8430
Modified:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
following the resets properly
Modified:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/rx_buffer_inband.v
2008-05-15 15:57:21 UTC (rev 8429)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/rx_buffer_inband.v
2008-05-15 17:43:55 UTC (rev 8430)
@@ -5,6 +5,7 @@
input bus_reset,
input reset, // DSP side reset (used here), do not reset registers
input reset_regs, //Only reset registers
+ input clock_reset,
output [15:0] usbdata,
input RD,
output wire have_pkt_rdy,
@@ -53,7 +54,7 @@
// Time counter
reg [31:0] timestamp_clock;
always @(posedge rxclk)
- if (reset)
+ if (clock_reset)
timestamp_clock <= 0;
else
timestamp_clock <= timestamp_clock + 1;
Modified:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/tx_buffer_inband.v
2008-05-15 15:57:21 UTC (rev 8429)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/tx_buffer_inband.v
2008-05-15 17:43:55 UTC (rev 8430)
@@ -1,6 +1,6 @@
module tx_buffer_inband
( //System
- input wire usbclk, input wire bus_reset, input wire reset,
+ input wire usbclk, input wire bus_reset, input wire reset, input wire
clock_reset,
input wire [15:0] usbdata, output wire have_space, input wire [3:0]
channels,
//output transmit signals
output wire [15:0] tx_i_0, output wire [15:0] tx_q_0,
@@ -37,7 +37,7 @@
assign rssi[3] = rssi_3;
always @(posedge txclk)
- if (reset)
+ if (clock_reset)
timestamp_clock <= 0;
else
timestamp_clock <= timestamp_clock + 1;
Modified:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2008-05-15 15:57:21 UTC (rev 8429)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2008-05-15 17:43:55 UTC (rev 8430)
@@ -420,4 +420,5 @@
set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_ram.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/register_io.v
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
\ No newline at end of file
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
\ No newline at end of file
Modified:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2008-05-15 15:57:21 UTC (rev 8429)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2008-05-15 17:43:55 UTC (rev 8430)
@@ -132,7 +132,7 @@
`ifdef TX_IN_BAND
tx_buffer_inband tx_buffer
- ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
+ (
.usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),.clock_reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),
.tx_underrun(tx_underrun),.channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
@@ -258,7 +258,7 @@
.ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan));
`ifdef RX_IN_BAND
rx_buffer_inband rx_buffer
- ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
+ (
.usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),.clock_reset(tx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
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