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[Commit-gnuradio] r8532 - usrp2/trunk/fpga/sdr_lib
From: |
matt |
Subject: |
[Commit-gnuradio] r8532 - usrp2/trunk/fpga/sdr_lib |
Date: |
Wed, 28 May 2008 18:45:07 -0600 (MDT) |
Author: matt
Date: 2008-05-28 18:45:03 -0600 (Wed, 28 May 2008)
New Revision: 8532
Added:
usrp2/trunk/fpga/sdr_lib/hb_interp.v
usrp2/trunk/fpga/sdr_lib/small_hb_int.v
Log:
first cut a halfband interpolators, don't work except for passthru mode yet,
not yet included in dsp_core_tx.v
Added: usrp2/trunk/fpga/sdr_lib/hb_interp.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/hb_interp.v (rev 0)
+++ usrp2/trunk/fpga/sdr_lib/hb_interp.v 2008-05-29 00:45:03 UTC (rev
8532)
@@ -0,0 +1,28 @@
+// Short halfband decimator (intended to be followed by another stage)
+// Implements impulse responses of the form [A 0 B 0.5 B 0 A]
+//
+// These taps designed by halfgen4 from ldoolittle:
+// 2 * 131072 * halfgen4(.75/8,2)
+module hb_interp
+ #(parameter WIDTH=18)
+ (input clk,
+ input rst,
+ input bypass,
+ input stb_in,
+ input [WIDTH-1:0] data_in,
+ output reg stb_out,
+ output reg [WIDTH-1:0] data_out);
+
+ always @(posedge clk)
+ if(bypass)
+ data_out <= data_in;
+ else
+ data_out <= 0;
+
+ always @(posedge clk)
+ if(bypass)
+ stb_out <= stb_in;
+ else
+ stb_out <= 0;
+
+endmodule // hb_interp
Added: usrp2/trunk/fpga/sdr_lib/small_hb_int.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/small_hb_int.v (rev 0)
+++ usrp2/trunk/fpga/sdr_lib/small_hb_int.v 2008-05-29 00:45:03 UTC (rev
8532)
@@ -0,0 +1,74 @@
+// Short halfband decimator (intended to be followed by another stage)
+// Implements impulse responses of the form [A 0 B 0.5 B 0 A]
+//
+// These taps designed by halfgen4 from ldoolittle:
+// 2 * 131072 * halfgen4(.75/8,2)
+module small_hb_int
+ #(parameter WIDTH=18)
+ (input clk,
+ input rst,
+ input bypass,
+ input stb_in,
+ input [WIDTH-1:0] data_in,
+ output reg stb_out,
+ output reg [WIDTH-1:0] data_out);
+
+ reg [WIDTH-1:0] filt_out;
+ reg filt_out_stb;
+ reg odd;
+ reg [WIDTH-1:0] d1, d2, d3, d4;
+
+ localparam MWIDTH = 36;
+ wire [MWIDTH-1:0] prod;
+
+ always @(posedge clk)
+ if(stb_in)
+ begin
+ d1 <= data_in;
+ d2 <= d1;
+ d3 <= d2;
+ d4 <= d3;
+ end
+
+ wire [WIDTH-1:0] sum_outer, sum_inner;
+ add2_and_round_reg #(.WIDTH(WIDTH)) add_outer
(.clk(clk),.in1(d1),.in2(d4),.sum(sum_outer));
+ add2_and_round_reg #(.WIDTH(WIDTH)) add_inner
(.clk(clk),.in1(d2),.in2(d3),.sum(sum_inner));
+
+ wire [17:0] coeff_outer = -10690;
+ wire [17:0] coeff_inner = 75809;
+ reg phase = 0;
+ MULT18X18S mult(.C(clk), .CE(1), .R(rst), .P(prod), .A(phase ? coeff_outer
: coeff_inner), .B(phase ? sum_outer : sum_inner) );
+
+ wire [MWIDTH:0] accum;
+ acc #(.IWIDTH(MWIDTH),.OWIDTH(MWIDTH+1))
+ acc (.clk(clk),.clear(),.acc(),.in(prod),.out(accum));
+
+ wire [17:0] accum_rnd;
+ round_reg #(.bits_in(MWIDTH+1),.bits_out(WIDTH))
+ final_round (.clk(clk),.in(accum),.out(accum_rnd));
+
+ always @(posedge clk)
+ filt_out <= phase ? accum_rnd : d3;
+
+ always @(posedge clk)
+ if(rst)
+ odd <= 0;
+ else if(stb_out)
+ odd <= ~odd;
+
+ always @(posedge clk)
+ if(bypass)
+ data_out <= data_in;
+ else
+ data_out <= filt_out;
+
+ always @(posedge clk)
+ if(bypass)
+ stb_out <= stb_in;
+ else
+ stb_out <= filt_out_stb;
+
+
+
+endmodule // small_hb_int
+
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