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[Commit-gnuradio] r8823 - usrp2/trunk/fpga/sdr_lib
From: |
matt |
Subject: |
[Commit-gnuradio] r8823 - usrp2/trunk/fpga/sdr_lib |
Date: |
Mon, 7 Jul 2008 19:45:41 -0600 (MDT) |
Author: matt
Date: 2008-07-07 19:45:40 -0600 (Mon, 07 Jul 2008)
New Revision: 8823
Modified:
usrp2/trunk/fpga/sdr_lib/dsp_core_tx.v
Log:
refactored strobes
Modified: usrp2/trunk/fpga/sdr_lib/dsp_core_tx.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/dsp_core_tx.v 2008-07-08 01:45:20 UTC (rev
8822)
+++ usrp2/trunk/fpga/sdr_lib/dsp_core_tx.v 2008-07-08 01:45:40 UTC (rev
8823)
@@ -11,17 +11,18 @@
// To tx_control
input [31:0] sample,
input run,
- output strobe
+ output strobe,
+ output [31:0] debug
);
-
+
wire [15:0] i, q, scale_i, scale_q;
wire [31:0] phase_inc;
reg [31:0] phase;
wire [7:0] interp_rate;
wire strobe_cic, strobe_hb1, strobe_hb2;
- assign strobe = strobe_hb2;
wire enable_hb1, enable_hb2;
+ assign debug = {strobe_cic, strobe_hb1, strobe_hb2,run};
setting_reg #(.my_addr(`DSP_CORE_TX_BASE+0)) sr_0
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -33,11 +34,22 @@
setting_reg #(.my_addr(`DSP_CORE_TX_BASE+2)) sr_2
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out({/*enable_hb1,enable_hb2, */
interp_rate}),.changed());
+ .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed());
- assign enable_hb1 = 0;
- assign enable_hb2 = 0;
+ wire [8:0] total_interp_rate = (enable_hb1 & enable_hb2) ?
{interp_rate,2'b0} :
+ (enable_hb1 | enable_hb2) ? {interp_rate,1'b0} :
+ {1'b0,interp_rate};
+ cic_strober #(.WIDTH(8))
+ cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
+ .strobe_fast(1),.strobe_slow(strobe_cic) );
+ cic_strober #(.WIDTH(2))
+ hb2_strober(.clock(clk),.reset(rst),.enable(run),.rate(enable_hb2 ? 2 :
1),
+ .strobe_fast(strobe_cic),.strobe_slow(strobe_hb2) );
+ cic_strober #(.WIDTH(2))
+ hb1_strober(.clock(clk),.reset(rst),.enable(run),.rate(enable_hb1 ? 2 :
1),
+ .strobe_fast(strobe_hb2),.strobe_slow(strobe_hb1) );
+
always @(posedge clk)
if(rst)
phase <= 0;
@@ -54,18 +66,17 @@
wire [17:0] hb1_i, hb1_q, hb2_i, hb2_q;
hb_interp #(.WIDTH(18)) hb_interp_i
-
(.clk(clk),.rst(rst),.bypass(~enable_hb1),.stb_in(strobe_hb2),.data_in(bb_i),.stb_out(strobe_hb1),.data_out(hb1_i));
+
(.clk(clk),.rst(rst),.bypass(~enable_hb1),.stb_in(strobe_hb1),.data_in(bb_i),.stb_out(strobe_hb2),.data_out(hb1_i));
hb_interp #(.WIDTH(18)) hb_interp_q
-
(.clk(clk),.rst(rst),.bypass(~enable_hb1),.stb_in(strobe_hb2),.data_in(bb_q),.stb_out(),.data_out(hb1_q));
+
(.clk(clk),.rst(rst),.bypass(~enable_hb1),.stb_in(strobe_hb1),.data_in(bb_q),.stb_out(strobe_hb2),.data_out(hb1_q));
small_hb_int #(.WIDTH(18)) small_hb_interp_i
-
(.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_cic),.data_in(hb1_i),.stb_out(strobe_hb2),.data_out(hb2_i));
+
(.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_i),
+ .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_i));
small_hb_int #(.WIDTH(18)) small_hb_interp_q
-
(.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_cic),.data_in(hb1_q),.stb_out(),.data_out(hb2_q));
+
(.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_q),
+ .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_q));
- cic_strober
cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
- .strobe_fast(1),.strobe_slow(strobe_cic) );
-
cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7))
cic_interp_i(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
.strobe_in(strobe_cic),.strobe_out(1),
@@ -76,7 +87,8 @@
.strobe_in(strobe_cic),.strobe_out(1),
.signal_in(hb2_q),.signal_out(q_interp));
-
+ assign strobe = strobe_hb1;
+
cordic #(.bitwidth(18),.zwidth(16))
cordic(.clock(clk), .reset(rst), .enable(run),
.xi(i_interp),.yi(q_interp),.zi(phase[31:16]),
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