[Commit-gnuradio] r8905 - usrp2/trunk/fpga/top/u2_rev3

[matt]

Author: matt
Date: 2008-07-16 14:12:56 -0600 (Wed, 16 Jul 2008)
New Revision: 8905

Modified:
   usrp2/trunk/fpga/top/u2_rev3/Makefile
Log:
catch up with rev2 changes


Modified: usrp2/trunk/fpga/top/u2_rev3/Makefile
===================================================================
--- usrp2/trunk/fpga/top/u2_rev3/Makefile       2008-07-16 19:26:28 UTC (rev 
8904)
+++ usrp2/trunk/fpga/top/u2_rev3/Makefile       2008-07-16 20:12:56 UTC (rev 
8905)
@@ -22,13 +22,14 @@
 ##################################################
 # xtclsh Shell and tcl Script Path
 ##################################################
-XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
-ISE_HELPER := $(shell pwd)/../tcl/ise_helper.tcl
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
 
 ##################################################
 # Project Setup
 ##################################################
-BUILD_DIR := $(shell pwd)/build/
+BUILD_DIR := build/
 export TOP_MODULE := u2_rev3
 export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
 
@@ -50,7 +51,7 @@
 ##################################################
 # Sources
 ##################################################
-export SOURCE_ROOT := $(shell pwd)/../../
+export SOURCE_ROOT := ../../../
 export SOURCES := \
 control_lib/CRC16_D16.v \
 control_lib/atr_controller.v \
@@ -85,7 +86,10 @@
 control_lib/simple_uart.v \
 control_lib/simple_uart_tx.v \
 control_lib/simple_uart_rx.v \
-coregen/fifo_generator_v4_1.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
 eth/mac_rxfifo_int.v \
 eth/mac_txfifo_int.v \
 eth/rtl/verilog/Clk_ctrl.v \
@@ -186,13 +190,13 @@
 "Use Synchronous Set" Auto
 
 export TRANSLATE_PROPERTIES := \
-"Macro Search Path" "$(SOURCE_ROOT)/coregen/"
+"Macro Search Path" "$(shell pwd)/../../coregen/"
 
 export MAP_PROPERTIES := \
 "Allow Logic Optimization Across Hierarchy" TRUE \
 "Map to Input Functions" 4 \
 "Optimization Strategy (Cover Mode)" Speed \
-"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" 
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
 "Perform Timing-Driven Packing and Placement" TRUE \
 "Map Effort Level" High \
 "Extra Effort" Normal \