[Commit-gnuradio] r8920 - usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx

[matt]

Author: matt
Date: 2008-07-17 12:32:06 -0600 (Thu, 17 Jul 2008)
New Revision: 8920

Modified:
   usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/CRC_gen.v
Log:
remove unnecessary reset to fix a timing problem.  Also removed unnecessary 
gating of output.


Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/CRC_gen.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/CRC_gen.v   2008-07-17 18:30:09 UTC 
(rev 8919)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/CRC_gen.v   2008-07-17 18:32:06 UTC 
(rev 8920)
@@ -122,18 +122,19 @@
         endfunction
 
//******************************************************************************
 
-always @ (posedge Clk or posedge Reset)
-    if (Reset)
+always @ (posedge Clk) // or posedge Reset)
+//    if (Reset)
+//        CRC_reg     <=32'hffffffff;
+//    else 
+    if (Init)
         CRC_reg     <=32'hffffffff;
-    else if (Init)
-        CRC_reg     <=32'hffffffff;
     else if (Data_en)
         CRC_reg     <=NextCRC(Frame_data,CRC_reg);
     else if (CRC_rd)
         CRC_reg     <={CRC_reg[23:0],8'hff};
         
 always @ (CRC_rd or CRC_reg)
-    if (CRC_rd)
+//    if (CRC_rd)
         CRC_out     <=~{
                         CRC_reg[24],
                         CRC_reg[25],
@@ -144,8 +145,8 @@
                         CRC_reg[30],
                         CRC_reg[31]
                         };
-    else
-        CRC_out     <=0;
+//    else
+//        CRC_out     <=0;
         
 //caculate CRC out length ,4 cycles     
 //CRC_end aligned to last CRC checksum data