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[Commit-gnuradio] r9004 - in usrp2/branches/features/host-ng/firmware: a
|
From: |
eb |
|
Subject: |
[Commit-gnuradio] r9004 - in usrp2/branches/features/host-ng/firmware: apps include lib |
|
Date: |
Thu, 24 Jul 2008 14:10:02 -0600 (MDT) |
Author: eb
Date: 2008-07-24 14:09:56 -0600 (Thu, 24 Jul 2008)
New Revision: 9004
Added:
usrp2/branches/features/host-ng/firmware/apps/echo.c
usrp2/branches/features/host-ng/firmware/include/usrp2_mimo_config.h
usrp2/branches/features/host-ng/firmware/lib/clocks.c
usrp2/branches/features/host-ng/firmware/lib/clocks.h
Modified:
usrp2/branches/features/host-ng/firmware/apps/
usrp2/branches/features/host-ng/firmware/apps/Makefile.am
usrp2/branches/features/host-ng/firmware/apps/app_common_v2.c
usrp2/branches/features/host-ng/firmware/include/usrp2_eth_packet.h
usrp2/branches/features/host-ng/firmware/lib/Makefile.am
usrp2/branches/features/host-ng/firmware/lib/db_rfx.c
usrp2/branches/features/host-ng/firmware/lib/hal_io.c
usrp2/branches/features/host-ng/firmware/lib/hal_uart.c
usrp2/branches/features/host-ng/firmware/lib/memory_map.h
usrp2/branches/features/host-ng/firmware/lib/stdio.h
usrp2/branches/features/host-ng/firmware/lib/u2_init.c
Log:
Merged eb/fw-merge -r9002:9003 into features/host-ng. The net effect
of this is to merge trunk/firmware -r8608:8997 into
features/host-ng/firmware. Thus, features/host-ng/firmware now
contains all the latest firmware features and requires an FPGA image
built from trunk/fpga. (We'll get the rest of this mess merged RSN.)
Property changes on: usrp2/branches/features/host-ng/firmware/apps
___________________________________________________________________
Name: svn:ignore
- *-stamp
*.a
*.bin
*.dump
*.log
*.rom
*.map
.deps
Makefile
Makefile.in
aclocal.m4
autom4te.cache
blink_leds
blink_leds2
build
compile
config.h
config.h.in
config.log
config.status
configure
depcomp
eth_test
gen_eth_packets
ibs_rx_test
ibs_tx_test
install-sh
libtool
ltmain.sh
missing
py-compile
rcv_eth_packets
run_tests.sh
stamp-h1
test1
test_phy_comm
timer_test
buf_ram_test
buf_ram_zero
hello
test_printf
test_spi
test_i2c
gen_pause_frames
test_serdes
rx_only
tx_only
tx_standalone
tx_drop
tx_drop2
tx_drop_rate_limited
test_lsdac
test_lsadc
read_dbids
test_db_spi
ramp_lsdac
eth_to_serdes
serdes_to_dsp
sd_gentest
sd_bounce
can_i_sub
tx_only_v2
rx_only_v2
txrx
+ *-stamp
*.a
*.bin
*.dump
*.log
*.rom
*.map
.deps
Makefile
Makefile.in
aclocal.m4
autom4te.cache
blink_leds
blink_leds2
build
compile
config.h
config.h.in
config.log
config.status
configure
depcomp
echo
eth_test
gen_eth_packets
ibs_rx_test
ibs_tx_test
install-sh
libtool
ltmain.sh
missing
py-compile
rcv_eth_packets
run_tests.sh
stamp-h1
test1
test_phy_comm
timer_test
buf_ram_test
buf_ram_zero
hello
test_printf
test_spi
test_i2c
gen_pause_frames
test_serdes
rx_only
tx_only
tx_standalone
tx_drop
tx_drop2
tx_drop_rate_limited
test_lsdac
test_lsadc
read_dbids
test_db_spi
ramp_lsdac
eth_to_serdes
serdes_to_dsp
sd_gentest
sd_bounce
can_i_sub
tx_only_v2
rx_only_v2
txrx
Modified: usrp2/branches/features/host-ng/firmware/apps/Makefile.am
===================================================================
--- usrp2/branches/features/host-ng/firmware/apps/Makefile.am 2008-07-24
20:00:39 UTC (rev 9003)
+++ usrp2/branches/features/host-ng/firmware/apps/Makefile.am 2008-07-24
20:09:56 UTC (rev 9004)
@@ -24,6 +24,7 @@
blink_leds2 \
buf_ram_test \
can_i_sub \
+ echo \
gen_eth_packets \
hello \
ibs_rx_test \
Modified: usrp2/branches/features/host-ng/firmware/apps/app_common_v2.c
===================================================================
--- usrp2/branches/features/host-ng/firmware/apps/app_common_v2.c
2008-07-24 20:00:39 UTC (rev 9003)
+++ usrp2/branches/features/host-ng/firmware/apps/app_common_v2.c
2008-07-24 20:09:56 UTC (rev 9004)
@@ -27,6 +27,7 @@
#include "nonstdio.h"
#include "print_rmon_regs.h"
#include "db.h"
+#include "clocks.h"
#include <string.h>
volatile bool link_is_up = false; // eth handler sets this
@@ -44,6 +45,13 @@
return ethernet_set_mac_addr(&p->addr);
}
+static bool
+config_mimo_cmd(const op_config_mimo_t *p)
+{
+ clocks_mimo_config(p->flags);
+ return true;
+}
+
void
set_reply_hdr(u2_eth_packet_t *reply_pkt, u2_eth_packet_t const *cmd_pkt)
{
@@ -139,10 +147,26 @@
}
if (p->valid & CFGV_INTERP_DECIM){
+ int interp = p->interp;
+ int hb1 = 0;
+ int hb2 = 0;
+
+ if (!(interp & 1)){
+ hb2 = 1;
+ interp = interp >> 1;
+ }
+
+ if (!(interp & 1)){
+ hb1 = 1;
+ interp = interp >> 1;
+ }
+
if (p->interp < MIN_INTERP || p->interp > MAX_INTERP)
ok = false;
- else
- dsp_tx_regs->interp_rate = p->interp;
+ else {
+ dsp_tx_regs->interp_rate = (hb1<<9) | (hb2<<8) | interp;
+ // printf("Interp: %d, register %d\n", p->interp, (hb1<<9) | (hb2<<8) |
interp);
+ }
}
if (p->valid & CFGV_SCALE_IQ){
@@ -335,6 +359,11 @@
burn_mac_addr((op_burn_mac_addr_t *) payload));
break;
+ case OP_CONFIG_MIMO:
+ subpktlen = generic_reply(gp, reply_payload, reply_payload_space,
+ config_mimo_cmd((op_config_mimo_t *) payload));
+ break;
+
case OP_READ_TIME:
subpktlen = read_time_cmd(gp, reply_payload, reply_payload_space);
break;
Copied: usrp2/branches/features/host-ng/firmware/apps/echo.c (from rev 9003,
usrp2/branches/developers/eb/fw-merge/firmware/apps/echo.c)
===================================================================
--- usrp2/branches/features/host-ng/firmware/apps/echo.c
(rev 0)
+++ usrp2/branches/features/host-ng/firmware/apps/echo.c 2008-07-24
20:09:56 UTC (rev 9004)
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2008 Free Software Foundation, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "u2_init.h"
+#include "stdio.h"
+
+int
+main(void)
+{
+ u2_init();
+
+ puts("\n>>> echo <<<");
+
+ while (1){
+ int ch = getchar();
+ putchar(ch);
+ }
+
+ return 0;
+}
Modified: usrp2/branches/features/host-ng/firmware/include/usrp2_eth_packet.h
===================================================================
--- usrp2/branches/features/host-ng/firmware/include/usrp2_eth_packet.h
2008-07-24 20:00:39 UTC (rev 9003)
+++ usrp2/branches/features/host-ng/firmware/include/usrp2_eth_packet.h
2008-07-24 20:09:56 UTC (rev 9004)
@@ -22,6 +22,7 @@
#include "usrp2_cdefs.h"
#include "usrp2_bytesex.h"
#include "usrp2_mac_addr.h"
+#include "usrp2_mimo_config.h"
__U2_BEGIN_DECLS
@@ -160,7 +161,6 @@
*
* Reply opcodes are the same as the request opcode with the OP_REPLY_BIT set
(0x80).
*/
-
#define OP_REPLY_BIT 0x80
#define OP_EOP 0 // marks last subpacket in
packet
@@ -179,7 +179,10 @@
#define OP_START_RX_STREAMING_REPLY (OP_START_RX_STREAMING |
OP_REPLY_BIT)
#define OP_STOP_RX 7
#define OP_STOP_RX_REPLY (OP_STOP_RX | OP_REPLY_BIT)
+#define OP_CONFIG_MIMO 8
+#define OP_CONFIG_MIMO_REPLY (OP_CONFIG_MIMO | OP_REPLY_BIT)
+
//#define OP_WRITE_REG xx // not implemented
//#define OP_WRITE_REG_MASKED xx
//#define OP_READ_REG xx
@@ -334,7 +337,17 @@
} _AL4 op_config_tx_reply_v2_t;
+/*!
+ * \brief Configure MIMO clocking, etc (uses generic reply)
+ */
+typedef struct {
+ uint8_t opcode;
+ uint8_t len;
+ uint8_t rid;
+ uint8_t flags; // from usrp_mimo_config.h
+} op_config_mimo_t;
+
/*
* ================================================================
* union of all of subpacket types
@@ -351,6 +364,7 @@
op_config_rx_reply_v2_t op_config_rx_reply_v2;
op_config_tx_v2_t op_config_tx_v2;
op_config_tx_reply_v2_t op_config_tx_reply_v2;
+ op_config_mimo_t op_config_mimo;
} u2_subpkt_t;
Copied: usrp2/branches/features/host-ng/firmware/include/usrp2_mimo_config.h
(from rev 9003,
usrp2/branches/developers/eb/fw-merge/firmware/include/usrp2_mimo_config.h)
===================================================================
--- usrp2/branches/features/host-ng/firmware/include/usrp2_mimo_config.h
(rev 0)
+++ usrp2/branches/features/host-ng/firmware/include/usrp2_mimo_config.h
2008-07-24 20:09:56 UTC (rev 9004)
@@ -0,0 +1,46 @@
+/* -*- c -*- */
+/*
+ * Copyright 2008 Free Software Foundation, Inc.
+ *
+ * This file is part of GNU Radio
+ *
+ * GNU Radio is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ *
+ * GNU Radio is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef INCLUDED_USRP2_MIMO_CONFIG_H
+#define INCLUDED_USRP2_MIMO_CONFIG_H
+
+#define _MC_WE_LOCK 0x0001
+#define _MC_MIMO_CLK_INPUT 0x0002 // else SMA
input
+
+/*
+ * Derived masks (use these):
+ *
+ * We get our input from 1 of three places:
+ * Our free running oscilator, our SMA connector, or from the MIMO connector
+ */
+#define MC_WE_DONT_LOCK 0x0000
+#define MC_WE_LOCK_TO_SMA (_MC_WE_LOCK | 0)
+#define MC_WE_LOCK_TO_MIMO (_MC_WE_LOCK |
_MC_MIMO_CLK_INPUT)
+
+/*
+ * Independent of the source of the clock, we may or may not drive our
+ * clock onto the mimo connector. Note that there are dedicated clock
+ * signals in each direction, so disaster doesn't occurs if we're
+ * unnecessarily providing clock.
+ */
+#define MC_PROVIDE_CLK_TO_MIMO 0x0004
+
+
+#endif /* INCLUDED_USRP2_MIMO_CONFIG_H */
Modified: usrp2/branches/features/host-ng/firmware/lib/Makefile.am
===================================================================
--- usrp2/branches/features/host-ng/firmware/lib/Makefile.am 2008-07-24
20:00:39 UTC (rev 9003)
+++ usrp2/branches/features/host-ng/firmware/lib/Makefile.am 2008-07-24
20:09:56 UTC (rev 9004)
@@ -20,10 +20,12 @@
noinst_LIBRARIES = \
libu2fw.a
+
libu2fw_a_SOURCES = \
ad9510.c \
ad9777.c \
buffer_pool.c \
+ clocks.c \
db_basic.c \
db_init.c \
db_rfx.c \
@@ -48,3 +50,35 @@
printf.c \
spi.c \
u2_init.c
+
+
+noinst_HEADERS = \
+ ad9510.h \
+ ad9777.h \
+ ad9777_regs.h \
+ bool.h \
+ buffer_pool.h \
+ clocks.h \
+ db.h \
+ db_base.h \
+ dbsm.h \
+ eth_mac.h \
+ eth_mac_regs.h \
+ eth_phy.h \
+ ethernet.h \
+ hal_io.h \
+ hal_uart.h \
+ i2c.h \
+ lsadc.h \
+ lsdac.h \
+ mdelay.h \
+ memcpy_wa.h \
+ memory_map.h \
+ memset_wa.h \
+ nonstdio.h \
+ pic.h \
+ print_rmon_regs.h \
+ spi.h \
+ stdint.h \
+ stdio.h \
+ u2_init.h
Copied: usrp2/branches/features/host-ng/firmware/lib/clocks.c (from rev 9003,
usrp2/branches/developers/eb/fw-merge/firmware/lib/clocks.c)
===================================================================
--- usrp2/branches/features/host-ng/firmware/lib/clocks.c
(rev 0)
+++ usrp2/branches/features/host-ng/firmware/lib/clocks.c 2008-07-24
20:09:56 UTC (rev 9004)
@@ -0,0 +1,182 @@
+/* -*- c++ -*- */
+/*
+ * Copyright 2008 Free Software Foundation, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include <config.h>
+#endif
+#include <clocks.h>
+
+#include "memory_map.h"
+#include "ad9510.h"
+#include "spi.h"
+
+void
+clocks_init(void)
+{
+ // Set up basic clocking functions in AD9510
+ ad9510_write_reg(0x45, 0x00); // CLK2 drives distribution
+ ad9510_write_reg(0x3D, 0x00); // Turn on output 1 (FPGA CLK), normal levels
+ ad9510_write_reg(0x4B, 0x80); // Bypass divider 1
+ ad9510_write_reg(0x5A, 0x01); // Update Regs
+
+ spi_wait();
+
+ // Set up PLL for 10 MHz reference
+ // Reg 4, A counter, Don't Care
+ ad9510_write_reg(0x05, 0x00); // Reg 5, B counter MSBs, 0
+ ad9510_write_reg(0x06, 0x05); // Reg 6, B counter LSBs, 5
+ // Reg 7, Loss of reference detect, doesn't work yet, 0
+ ad9510_write_reg(0x5A, 0x01); // Update Regs
+
+
+ // FIXME, probably need interface to this...
+ timesync_regs->tick_control = 4;
+
+ // Primary clock configuration
+ clocks_mimo_config(MC_WE_DONT_LOCK);
+
+ // Set up other clocks
+
+ clocks_enable_test_clk(false);
+ clocks_enable_tx_dboard(false, 0);
+ clocks_enable_rx_dboard(false, 0);
+
+ // ETH phy clock
+ ad9510_write_reg(0x41, 0x01); // Turn off output 5 (phy_clk)
+ ad9510_write_reg(0x53, 0x80); // Bypass divider
+ ad9510_write_reg(0x5A, 0x01); // Update Regs
+
+ // Enable clock to ADCs and DACs
+ ad9510_write_reg(0x3F, 0x00); // Turn on output 3 (DAC CLK), normal levels
+ ad9510_write_reg(0x4F, 0x80); // Bypass Div #3
+
+ ad9510_write_reg(0x40, 0x02); // Turn on out 4 (ADC clk), LVDS
+ ad9510_write_reg(0x51, 0x80); // Bypass Div #4
+
+ ad9510_write_reg(0x5A, 0x01); // Update Regs
+}
+
+
+void
+clocks_mimo_config(int flags)
+{
+ if (flags & _MC_WE_LOCK){
+ // Reg 8, Charge pump on, dig lock det, positive PFD, 47
+ ad9510_write_reg(0x08, 0x47);
+ }
+ else {
+ // Reg 8, Charge pump off, dig lock det, positive PFD
+ ad9510_write_reg(0x08, 0x00);
+ }
+
+ // Reg 9, Charge pump current, 0x40=3mA, 0x00=650uA
+ ad9510_write_reg(0x09, 0x00);
+ // Reg A, Prescaler of 2, everything normal 04
+ ad9510_write_reg(0x0A, 0x04);
+ // Reg B, R Div MSBs, 0
+ ad9510_write_reg(0x0B, 0x00);
+ // Reg C, R Div LSBs, 1
+ ad9510_write_reg(0x0C, 0x01);
+ // Reg D, Antibacklash, Digital lock det, 0
+
+ ad9510_write_reg(0x5A, 0x01); // Update Regs
+
+ spi_wait();
+
+ // Allow for clock switchover
+
+ if (flags & _MC_WE_LOCK){ // WE LOCK
+ if (flags & _MC_MIMO_CLK_INPUT) {
+ // Turn on ref output and choose the MIMO connector
+ output_regs->clk_ctrl = 0x15;
+ }
+ else {
+ // turn on ref output and choose the SMA
+ output_regs->clk_ctrl = 0x1C;
+ }
+ }
+ else { // WE DONT LOCK
+ // Disable both ext clk inputs
+ output_regs->clk_ctrl = 0x10;
+ }
+
+ // Do we drive a clock onto the MIMO connector?
+
+ if (flags & MC_PROVIDE_CLK_TO_MIMO) {
+ ad9510_write_reg(0x3E, 0x00); // Turn on output 2 (clk_exp_out), normal
levels
+ ad9510_write_reg(0x4D, 0x00); // Turn on Div2
+ ad9510_write_reg(0x4C, 0x44); // Set Div2 = 10, output a 10 MHz clock
+ }
+ else {
+ ad9510_write_reg(0x3E, 0x02); // Turn off output 2 (clk_exp_out)
+ ad9510_write_reg(0x4D, 0x80); // Bypass divider 2
+ }
+ ad9510_write_reg(0x5A, 0x01); // Update Regs
+}
+
+void
+clocks_enable_test_clk(bool enable)
+{
+ if (enable){
+ ad9510_write_reg(0x3C, 0x08); // Turn on output 0 -- Test output
+ ad9510_write_reg(0x49, 0x80); // Bypass divider 0
+ }
+ else {
+ ad9510_write_reg(0x3C, 0x02); // Turn off output 0
+ }
+ ad9510_write_reg(0x5A, 0x01); // Update Regs
+}
+
+
+void
+clocks_enable_rx_dboard(bool enable, int divisor)
+{
+ if (enable){
+ ad9510_write_reg(0x43, 0x08); // enable output 7 (db_rx_clk), CMOS
+
+ if (divisor == 0){
+ ad9510_write_reg(0x57, 0x80); // Bypass Div #7, 100 MHz clock
+ }
+ else {
+ // FIXME Matt, do something with divisor...
+ }
+ }
+ else {
+ ad9510_write_reg(0x43, 0x01); // Turn off output 7 (db_rx_clk)
+ }
+ ad9510_write_reg(0x5A, 0x01); // Update Regs
+}
+
+
+void
+clocks_enable_tx_dboard(bool enable, int divisor)
+{
+ if (enable){
+ ad9510_write_reg(0x42, 0x08); // enable output 6 (db_tx_clk), CMOS
+ if (divisor == 0) {
+ ad9510_write_reg(0x55, 0x80); // Bypass Div #6, 100 MHz clock
+ }
+ else {
+ // FIXME Matt, do something with divisor
+ }
+ }
+ else {
+ ad9510_write_reg(0x42, 0x01); // Turn off output 6 (db_tx_clk)
+ }
+ ad9510_write_reg(0x5A, 0x01); // Update Regs
+}
Copied: usrp2/branches/features/host-ng/firmware/lib/clocks.h (from rev 9003,
usrp2/branches/developers/eb/fw-merge/firmware/lib/clocks.h)
===================================================================
--- usrp2/branches/features/host-ng/firmware/lib/clocks.h
(rev 0)
+++ usrp2/branches/features/host-ng/firmware/lib/clocks.h 2008-07-24
20:09:56 UTC (rev 9004)
@@ -0,0 +1,63 @@
+/* -*- c++ -*- */
+/*
+ * Copyright 2008 Free Software Foundation, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef INCLUDED_CLOCKS_H
+#define INCLUDED_CLOCKS_H
+
+/*
+ * Routines to configure our multitude of clocks
+ */
+
+#include <bool.h>
+#include <usrp2_mimo_config.h>
+
+
+/*!
+ * One time call to initialize all clocks to a reasonable state. We
+ * come out of here using our free running 100MHz oscilator and not
+ * providing a clock to the MIMO connector (CMC_WE_DONT_LOCK)
+ */
+void clocks_init(void);
+
+
+/*!
+ * \brief MIMO clock configuration.
+ *
+ * Configure our master clock source, and whether or not we drive a
+ * clock onto the mimo connector. See MC_flags in usrp2_mimo_config.h.
+ */
+void clocks_mimo_config(int flags);
+
+/*!
+ * \brief Enable or disable test clock (extra clock signal)
+ */
+void clocks_enable_test_clk(bool enable);
+
+/*!
+ * \brief Enable or disable clock to Rx daughterboard
+ */
+void clocks_enable_rx_dboard(bool enable, int divisor);
+
+
+/*!
+ * \brief Enable or disable clock to Tx daughterboard
+ */
+void clocks_enable_tx_dboard(bool enable, int divisor);
+
+
+#endif /* INCLUDED_CLOCKS_H */
Modified: usrp2/branches/features/host-ng/firmware/lib/db_rfx.c
===================================================================
--- usrp2/branches/features/host-ng/firmware/lib/db_rfx.c 2008-07-24
20:00:39 UTC (rev 9003)
+++ usrp2/branches/features/host-ng/firmware/lib/db_rfx.c 2008-07-24
20:09:56 UTC (rev 9004)
@@ -23,7 +23,9 @@
#include <stdio.h>
#include <mdelay.h>
#include <lsdac.h>
+#include <clocks.h>
+
bool rfx_init_rx(struct db_base *db);
bool rfx_init_tx(struct db_base *db);
bool rfx_set_freq(struct db_base *db, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc);
@@ -443,23 +445,19 @@
bool
rfx_init_tx(struct db_base *dbb)
{
- struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
- ad9510_write_reg(0x42, 0x08); // enable output 6 (db_tx_clk), CMOS
- ad9510_write_reg(0x55, 0x80); // Bypass Div #6, 100 MHz clock
- ad9510_write_reg(0x5A, 0x01); // Update Regs
+ //struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
+ clocks_enable_tx_dboard(true, 0);
return true;
}
bool
rfx_init_rx(struct db_base *dbb)
{
- struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
- ad9510_write_reg(0x43, 0x08); // enable output 7 (db_rx_clk), CMOS
- ad9510_write_reg(0x57, 0x80); // Bypass Div #7, 100 MHz clock
- ad9510_write_reg(0x5A, 0x01); // Update Regs
+ //struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
+ clocks_enable_rx_dboard(true, 0);
// test gain
- db->base.set_gain(db,U2_DOUBLE_TO_FXPT_GAIN(45.0));
+ dbb->set_gain(dbb,U2_DOUBLE_TO_FXPT_GAIN(45.0));
printf("set the gain\n");
return true;
}
@@ -551,6 +549,8 @@
{
struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
+ // FIXME
+
return false;
}
Modified: usrp2/branches/features/host-ng/firmware/lib/hal_io.c
===================================================================
--- usrp2/branches/features/host-ng/firmware/lib/hal_io.c 2008-07-24
20:00:39 UTC (rev 9003)
+++ usrp2/branches/features/host-ng/firmware/lib/hal_io.c 2008-07-24
20:09:56 UTC (rev 9004)
@@ -247,6 +247,12 @@
return ch;
}
+int
+getchar(void)
+{
+ return hal_uart_getc();
+}
+
#else // nop all i/o
void
@@ -266,6 +272,12 @@
return ch;
}
+int
+getchar(void)
+{
+ return EOF;
+}
+
#endif
// ================================================================
Modified: usrp2/branches/features/host-ng/firmware/lib/hal_uart.c
===================================================================
--- usrp2/branches/features/host-ng/firmware/lib/hal_uart.c 2008-07-24
20:00:39 UTC (rev 9003)
+++ usrp2/branches/features/host-ng/firmware/lib/hal_uart.c 2008-07-24
20:09:56 UTC (rev 9004)
@@ -18,7 +18,6 @@
#include "hal_uart.h"
#include "hal_io.h"
-#include "wb16550.h"
#include "memory_map.h"
// First pass, no interrupts
@@ -38,74 +37,31 @@
{ 163, 81, 41, 27, 14, 7 }, // 4: 25 MHz
};
-static hal_uart_config_t current_config;
-
-#define UART_LCR_8N1 (UART_LCR_WLEN8)
-
#define u uart_regs
void
hal_uart_init(void)
{
- u->ier = 0; // no interrupts enabled
- u->lcr = UART_LCR_8N1;
- u->iir_fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8 | UART_FCR_CLEAR_RCVR
| UART_FCR_CLEAR_XMIT;
- u->iir_fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8;
- u->mcr = 0;
-
- hal_uart_config_t c;
- c.speed = US_230400;
- hal_uart_set_config(&c);
+ u->clkdiv = 217; // 230400 bps
}
-void
-hal_uart_set_config(const hal_uart_config_t *c)
-{
- uint16_t divisor;
-
- if (c->speed >= NSPEEDS)
- return;
-
- current_config = *c;
-
- if (hwconfig_simulation_p()) // if we're simulating, go fast ;)
- divisor = 2;
- else {
- int t = hwconfig_wishbone_divisor();
- if (t > MAX_WB_DIV)
- t = MAX_WB_DIV;
- divisor = divisor_table[t][current_config.speed];
- }
-
- u->lcr = UART_LCR_8N1 | UART_LCR_DLAB; // enable access to divisor regs
- u->ier = (divisor >> 8); // write MSB first
- u->data = (divisor & 0xff); // then LSB
- u->lcr = UART_LCR_8N1; // back to normal mode
-}
-
void
-hal_uart_get_config(hal_uart_config_t *c)
-{
- *c = current_config;
-}
-
-void
hal_uart_putc(int ch)
{
if (ch == '\n') // FIXME for now map \n -> \r\n
hal_uart_putc('\r');
- while ((u->lsr & UART_LSR_THRE) == 0) // wait for fifo to be empty
+ while (u->txlevel == 0) // wait for fifo to have space
;
- u->data = ch;
+ u->txchar = ch;
}
int
hal_uart_getc(void)
{
- while ((u->lsr & UART_LSR_DR) == 0) // wait for data to be ready
+ while ((u->rxlevel) == 0) // wait for data to be ready
;
- return u->data;
+ return u->rxchar;
}
Modified: usrp2/branches/features/host-ng/firmware/lib/memory_map.h
===================================================================
--- usrp2/branches/features/host-ng/firmware/lib/memory_map.h 2008-07-24
20:00:39 UTC (rev 9003)
+++ usrp2/branches/features/host-ng/firmware/lib/memory_map.h 2008-07-24
20:09:56 UTC (rev 9004)
@@ -397,6 +397,7 @@
volatile uint32_t dcoffset_i; // Bit 31 high sets fixed offset mode,
using lower 14 bits,
// otherwise it is automatic
volatile uint32_t dcoffset_q; // Bit 31 high sets fixed offset mode,
using lower 14 bits
+ volatile uint32_t adc_mux; // 4 bits -- lowest 2 for adc_i, next
for adc_q
} dsp_rx_regs_t;
@@ -477,7 +478,8 @@
#define IRQ_UNDERRUN 5
#define IRQ_OVERRUN 6
#define IRQ_PPS 7 // pulse per second
-#define IRQ_UART 8
+#define IRQ_UART_RX 8
+#define IRQ_UART_TX 9
#define IRQ_TO_MASK(x) (1 << (x))
@@ -489,7 +491,8 @@
#define PIC_UNDERRUN_INT IRQ_TO_MASK(IRQ_UNDERRUN)
#define PIC_OVERRUN_INT IRQ_TO_MASK(IRQ_OVERRUN)
#define PIC_PPS_INT IRQ_TO_MASK(IRQ_PPS)
-#define PIC_UART_INT IRQ_TO_MASK(IRQ_UART)
+#define PIC_UART_RX_INT IRQ_TO_MASK(IRQ_UART_RX)
+#define PIC_UART_TX_INT IRQ_TO_MASK(IRQ_UART_TX)
typedef struct {
@@ -514,12 +517,21 @@
///////////////////////////////////////////////////
// UART, Slave 10
-// include "wb16650.h" for registers
#define UART_BASE 0xE000
-#define uart_regs ((wb16550_reg_t *) UART_BASE)
+typedef struct {
+ // All elements are 8 bits except for clkdiv (16), but we use uint32 to
make
+ // the hardware for decoding easier
+ volatile uint32_t clkdiv; // Set to 50e6 divided by baud rate (no x16
factor)
+ volatile uint32_t txlevel; // Number of spaces in the FIFO for writes
+ volatile uint32_t rxlevel; // Number of available elements in the FIFO for
reads
+ volatile uint32_t txchar; // Write characters to be sent here
+ volatile uint32_t rxchar; // Read received characters here
+} uart_regs_t;
+#define uart_regs ((uart_regs_t *) UART_BASE)
+
///////////////////////////////////////////////////
// ATR Controller, Slave 11
Modified: usrp2/branches/features/host-ng/firmware/lib/stdio.h
===================================================================
--- usrp2/branches/features/host-ng/firmware/lib/stdio.h 2008-07-24
20:00:39 UTC (rev 9003)
+++ usrp2/branches/features/host-ng/firmware/lib/stdio.h 2008-07-24
20:09:56 UTC (rev 9004)
@@ -33,6 +33,6 @@
int puts(const char *s);
int printf(const char *format, ...);
-// int getchar(void);
+int getchar(void);
#endif /* INCLUDED_STDIO_H */
Modified: usrp2/branches/features/host-ng/firmware/lib/u2_init.c
===================================================================
--- usrp2/branches/features/host-ng/firmware/lib/u2_init.c 2008-07-24
20:00:39 UTC (rev 9003)
+++ usrp2/branches/features/host-ng/firmware/lib/u2_init.c 2008-07-24
20:09:56 UTC (rev 9004)
@@ -28,7 +28,7 @@
#include "bool.h"
#include "mdelay.h"
#include "ad9777.h"
-#include "ad9510.h"
+#include "clocks.h"
#include "db.h"
//#include "nonstdio.h"
@@ -52,122 +52,12 @@
// init spi, so that we can switch over to the high-speed clock
spi_init();
- // Set up basic clocking functions in AD9510
- ad9510_write_reg(0x45, 0x00); // CLK2 drives distribution
- ad9510_write_reg(0x3D, 0x00); // Turn on output 1 (FPGA CLK), normal levels
- ad9510_write_reg(0x4B, 0x80); // Bypass divider 1
- ad9510_write_reg(0x5A, 0x01); // Update Regs
+ // set up the default clocks
+ clocks_init();
- spi_wait();
-
- // Set up PLL for 10 MHz reference
- // Reg 4, A counter, Don't Care
- ad9510_write_reg(0x05, 0x00); // Reg 5, B counter MSBs, 0
- ad9510_write_reg(0x06, 0x05); // Reg 6, B counter LSBs, 5
- // Reg 7, Loss of reference detect, doesn't work yet, 0
-
-#define LOCK_TO_EXT_REF 0
-#define LOCK_TO_MIMO_REF 0
-#define LOCK_NONE 1
-#define THEY_LOCK_TO_ME 0
-
- timesync_regs->tick_control = 4;
-
- // if(I WANT TO LOCK TO A REFERENCE CLOCK)
- if(LOCK_TO_EXT_REF || LOCK_TO_MIMO_REF) {
- // Reg 8, Charge pump on, dig lock det, positive PFD, 47
- ad9510_write_reg(0x08, 0x47);
- }
- else {
- // Reg 8, Charge pump off, dig lock det, positive PFD
- ad9510_write_reg(0x08, 0x00);
- }
-
- // Reg 9, Charge pump current, 0x40=3mA, 0x00=650uA
- ad9510_write_reg(0x09, 0x00);
- // Reg A, Prescaler of 2, everything normal 04
- ad9510_write_reg(0x0A, 0x04);
- // Reg B, R Div MSBs, 0
- ad9510_write_reg(0x0B, 0x00);
- // Reg C, R Div LSBs, 1
- ad9510_write_reg(0x0C, 0x01);
- // Reg D, Antibacklash, Digital lock det, 0
-
- ad9510_write_reg(0x5A, 0x01); // Update Regs
-
- spi_wait();
-
- // Allow for clock switchover
- if (LOCK_NONE) {
- // Disable both ext clk inputs
- output_regs->clk_ctrl = 0x10;
- }
- else if (LOCK_TO_EXT_REF) {
- // turn on ref output and choose the SMA
- output_regs->clk_ctrl = 0x1C;
- }
- else if (LOCK_TO_MIMO_REF) {
- // Turn on ref output and choose the MIMO connector
- output_regs->clk_ctrl = 0x15;
- }
-
-#define TEST_CLK 1
-#define REV2 1
-#define HACKED 0
-
- // Set up other clocks
- if(TEST_CLK) {
- ad9510_write_reg(0x3C, 0x08); // Turn on output 0 -- Test output
- ad9510_write_reg(0x49, 0x80); // Bypass divider 0
- } else {
- ad9510_write_reg(0x3C, 0x02); // Turn off output 0
- }
-
- if (THEY_LOCK_TO_ME) {
- ad9510_write_reg(0x3E, 0x00); // Turn on output 2 (clk_exp_out), normal
levels
- ad9510_write_reg(0x4D, 0x00); // Turn on Div2
- ad9510_write_reg(0x4C, 0x44); // Set Div2 = 10, output a 10 MHz clock
- }
- else {
- ad9510_write_reg(0x3E, 0x02); // Turn off output 2 (clk_exp_out)
- ad9510_write_reg(0x4D, 0x80); // Bypass divider 2
- }
-
- if(HACKED) { // Using the indirect ETH Clk
- ad9510_write_reg(0x41, 0x02); // Turn on output 5, LVDS
- ad9510_write_reg(0x52, 0x11); // Div by 4
- ad9510_write_reg(0x53, 0x0);
- }
- else if (REV2) {
- ad9510_write_reg(0x41, 0x01); // Turn off output 5 (phy_clk)
- ad9510_write_reg(0x53, 0x80); // Bypass divider
- }
- else {
- ad9510_write_reg(0x40, 0x01); // Turn off output 4 (phy_clk)
- ad9510_write_reg(0x51, 0x80); // Bypass divider
- }
-
- ad9510_write_reg(0x42, 0x01); // Turn off output 6 (db_tx_clk)
- ad9510_write_reg(0x43, 0x01); // Turn off output 7 (db_rx_clk)
- ad9510_write_reg(0x5A, 0x01); // Update Regs
-
// Enable ADCs
output_regs->adc_ctrl = ADC_CTRL_ON;
-
- // Enable clock to ADCs and DACs
- ad9510_write_reg(0x3F, 0x00); // Turn on output 3 (DAC CLK), normal levels
- ad9510_write_reg(0x4F, 0x80); // Bypass Div #3
- if (REV2) {
- //ad9510_write_reg(0x40, 0x08); // Turn on out 4 (ADC clk), CMOS
- ad9510_write_reg(0x40, 0x02); // Turn on out 4 (ADC clk), LVDS
- ad9510_write_reg(0x51, 0x80); // Bypass Div #4
- } else {
- ad9510_write_reg(0x41, 0x08); // Turn on out 5 (ADC clk), CMOS
- ad9510_write_reg(0x53, 0x80); // Bypass Div #5
- }
- ad9510_write_reg(0x5A, 0x01); // Update Regs
-
// Set up AD9777 DAC
ad9777_write_reg(0, R0_1R);
ad9777_write_reg(1, R1_INTERP_4X | R1_REAL_MIX);
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