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[Commit-gnuradio] r9048 - gnuradio/branches/developers/gnychis/fpga/usrp
From: |
gnychis |
Subject: |
[Commit-gnuradio] r9048 - gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches |
Date: |
Tue, 29 Jul 2008 14:06:35 -0600 (MDT) |
Author: gnychis
Date: 2008-07-29 14:06:34 -0600 (Tue, 29 Jul 2008)
New Revision: 9048
Modified:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tb_timestamps.v
Log:
fixing block format
Modified:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tb_timestamps.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tb_timestamps.v
2008-07-29 20:01:19 UTC (rev 9047)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tb_timestamps.v
2008-07-29 20:06:34 UTC (rev 9048)
@@ -81,16 +81,16 @@
#40 reset = 1'b0;
#40 bus_reset = 1'b0;
- end
+ end
always @(posedge rxclk)
begin
-
timestamp_clock <= timestamp_clock + 32'd1;
signal <= signal + 16'd1;
+ end
- begin
- @(posedge rxstrobe)
+ always @(posedge rxstrobe)
+ begin
ch_0 <= {signal,4'd0};
ch_1 <= {signal,4'd1};
ch_2 <= {signal,4'd2};
@@ -99,7 +99,6 @@
ch_5 <= {signal,4'd5};
ch_6 <= {signal,4'd6};
ch_7 <= {signal,4'd7};
- end
+ end
- end
endmodule
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- [Commit-gnuradio] r9048 - gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches,
gnychis <=