[Commit-gnuradio] r9092 - usrp2/trunk/fpga/control_lib

[matt]

Author: matt
Date: 2008-07-31 20:16:11 -0600 (Thu, 31 Jul 2008)
New Revision: 9092

Modified:
   usrp2/trunk/fpga/control_lib/medfifo.v
   usrp2/trunk/fpga/control_lib/simple_uart_rx.v
   usrp2/trunk/fpga/control_lib/simple_uart_tx.v
Log:
changes to match the 1-bit wider full/empty counters in the shortfifo


Modified: usrp2/trunk/fpga/control_lib/medfifo.v
===================================================================
--- usrp2/trunk/fpga/control_lib/medfifo.v      2008-08-01 02:15:00 UTC (rev 
9091)
+++ usrp2/trunk/fpga/control_lib/medfifo.v      2008-08-01 02:16:11 UTC (rev 
9092)
@@ -10,8 +10,8 @@
      input clear,
      output full,
      output empty,
-     output [3:0] space,
-     output [3:0] occupied);
+     output [7:0] space,
+     output [7:0] occupied);
 
    localparam          NUM_FIFOS = (1<<DEPTH);
    
@@ -23,13 +23,13 @@
      head (.clk(clk),.rst(rst),
           .datain(datain),.write(write),.full(full),
           .dataout(dout[0]),.read(~empty_x[0] & ~full_x[1]),.empty(empty_x[0]),
-          .clear(clear),.space(space),.occupied() );
+          .clear(clear),.space(space[4:0]),.occupied() );
    
    shortfifo #(.WIDTH(WIDTH))
      tail (.clk(clk),.rst(rst),
           .datain(dout[NUM_FIFOS-2]),.write(~empty_x[NUM_FIFOS-2] & 
~full_x[NUM_FIFOS-1]),.full(full_x[NUM_FIFOS-1]),
           .dataout(dataout),.read(read),.empty(empty),
-          .clear(clear),.space(),.occupied(occupied) );
+          .clear(clear),.space(),.occupied(occupied[4:0]) );
 
    genvar              i;
    generate
@@ -43,4 +43,7 @@
        end
    endgenerate
 
+   assign space[7:5] = 0;
+   assign occupied[7:5] = 0;
+   
 endmodule // medfifo

Modified: usrp2/trunk/fpga/control_lib/simple_uart_rx.v
===================================================================
--- usrp2/trunk/fpga/control_lib/simple_uart_rx.v       2008-08-01 02:15:00 UTC 
(rev 9091)
+++ usrp2/trunk/fpga/control_lib/simple_uart_rx.v       2008-08-01 02:16:11 UTC 
(rev 9092)
@@ -59,7 +59,6 @@
      (.clk(clk),.rst(rst),
       .datain(sr),.write(write),.full(full),
       .dataout(fifo_out),.read(fifo_read),.empty(fifo_empty),
-      .clear(0),.space(),.occupied(fifo_level[3:0]) );
-   assign        fifo_level[7:4] = 0;
+      .clear(0),.space(),.occupied(fifo_level) );
    
 endmodule // simple_uart_rx

Modified: usrp2/trunk/fpga/control_lib/simple_uart_tx.v
===================================================================
--- usrp2/trunk/fpga/control_lib/simple_uart_tx.v       2008-08-01 02:15:00 UTC 
(rev 9091)
+++ usrp2/trunk/fpga/control_lib/simple_uart_tx.v       2008-08-01 02:16:11 UTC 
(rev 9092)
@@ -15,8 +15,7 @@
      (.clk(clk),.rst(rst),
       .datain(fifo_in),.write(fifo_write),.full(fifo_full),
       .dataout(char_to_send),.read(read),.empty(empty),
-      .clear(0),.space(fifo_level[3:0]),.occupied() );
-   assign        fifo_level[7:4] = 0;
+      .clear(0),.space(fifo_level),.occupied() );
    
    always @(posedge clk)
      if(rst)