[Commit-gnuradio] r9093 - usrp2/trunk/fpga/control_lib

[matt]

Author: matt
Date: 2008-07-31 20:18:26 -0600 (Thu, 31 Jul 2008)
New Revision: 9093

Modified:
   usrp2/trunk/fpga/control_lib/longfifo.v
Log:
Fixed major bug in determining when the fifo is full.  The problem was with bit 
vectors being expanded quietly and signed math creeping in.


Modified: usrp2/trunk/fpga/control_lib/longfifo.v
===================================================================
--- usrp2/trunk/fpga/control_lib/longfifo.v     2008-08-01 02:16:11 UTC (rev 
9092)
+++ usrp2/trunk/fpga/control_lib/longfifo.v     2008-08-01 02:18:26 UTC (rev 
9093)
@@ -15,7 +15,8 @@
      input clear,
      output full,
      output empty,
-     output [15:0] fifo_space);
+     output [15:0] space,
+     output [15:0] occupied);
 
    // Read side states
    localparam    EMPTY = 0;
@@ -26,10 +27,12 @@
    reg [1:0]     read_state;
 
    wire [SIZE-1:0] fullness = wr_addr - rd_addr;  // Approximate, for 
simulation only
+   assign occupied = {{16-SIZE{1'b0}},fullness};
+
    wire [SIZE-1:0] free_space = rd_addr - wr_addr - 2;  // Approximate, for 
SERDES flow control
+   assign space = {{16-SIZE{1'b0}},free_space};
+         
    reg           empty_reg, full_reg;
-   assign fifo_space = {{16-SIZE{1'b0}},free_space};
-         
    always @(posedge clk)
      if(rst)
        wr_addr <= 0;
@@ -95,7 +98,10 @@
               else
                 rd_addr <= rd_addr + 1;
         endcase // case(read_state)
-   
+
+   wire [SIZE-1:0] dont_write_past_me = rd_addr - 3;
+   wire           becoming_full = wr_addr == dont_write_past_me;
+     
    always @(posedge clk)
      if(rst)
        full_reg <= 0;
@@ -103,7 +109,8 @@
        full_reg <= 0;
      else if(read & ~write)
        full_reg <= 0;
-     else if(write & ~read & (wr_addr == (rd_addr-3)))
+     //else if(write & ~read & (wr_addr == (rd_addr-3)))
+     else if(write & ~read & becoming_full)
        full_reg <= 1;
 
    //assign empty = (read_state != READING);